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Thumb disassembler did not handle tBRIND (indirect branch) properly.
rdar://problem/9280370 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -479,6 +479,7 @@ static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn,
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// tBX_RET: 0 operand
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// tBX_RET: 0 operand
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// tBX_RET_vararg: Rm
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// tBX_RET_vararg: Rm
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// tBLXr_r9: Rm
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// tBLXr_r9: Rm
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// tBRIND: Rm
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static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
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static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
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unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
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unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
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@ -486,14 +487,17 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
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if (NumOps == 0)
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if (NumOps == 0)
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return true;
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return true;
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// BX/BLX has 1 reg operand: Rm.
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// BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm.
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if (Opcode == ARM::tBLXr_r9 || Opcode == ARM::tBX_Rm) {
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if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX_Rm || Opcode==ARM::tBRIND) {
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// Handling the two predicate operands before the reg operand.
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if (Opcode != ARM::tBRIND) {
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if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
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// Handling the two predicate operands before the reg operand.
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return false;
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if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
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return false;
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NumOpsAdded += 2;
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}
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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getT1Rm(insn))));
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getT1Rm(insn))));
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NumOpsAdded = 3;
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NumOpsAdded += 1;
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return true;
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return true;
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}
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}
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@ -244,3 +244,6 @@
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# CHECK: mov.w r3, #4294967295
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# CHECK: mov.w r3, #4294967295
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0x4f 0xf0 0xff 0x33
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0x4f 0xf0 0xff 0x33
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# CHECK: mov pc, sp
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0xef 0x46
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