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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-18 10:24:45 +00:00
Remove more non-DebugLoc getNode variants. Use
getCALLSEQ_{END,START} to permit passing no DebugLoc there. UNDEF doesn't logically have DebugLoc; add getUNDEF to encapsulate this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63978 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -164,8 +164,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
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N->getExtensionType(),
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N->getValueType(0).getVectorElementType(),
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N->getChain(), N->getBasePtr(),
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DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
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N->getBasePtr().getValueType()),
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DAG.getUNDEF(N->getBasePtr().getValueType()),
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N->getSrcValue(), N->getSrcValueOffset(),
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N->getMemoryVT().getVectorElementType(),
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N->isVolatile(), N->getAlignment());
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@@ -203,16 +202,14 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
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return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
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N->getValueType(0).getVectorElementType());
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return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
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// Figure out if the scalar is the LHS or RHS and return it.
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SDValue Arg = N->getOperand(2).getOperand(0);
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if (Arg.getOpcode() == ISD::UNDEF)
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return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
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N->getValueType(0).getVectorElementType());
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return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
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unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
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return GetScalarizedVector(N->getOperand(Op));
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}
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@@ -632,7 +629,7 @@ void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
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DebugLoc dl = N->getDebugLoc();
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
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Hi = DAG.getNode(ISD::UNDEF, dl, HiVT);
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Hi = DAG.getUNDEF(HiVT);
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}
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void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
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@@ -645,7 +642,7 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
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ISD::LoadExtType ExtType = LD->getExtensionType();
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SDValue Ch = LD->getChain();
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SDValue Ptr = LD->getBasePtr();
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SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
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SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
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const Value *SV = LD->getSrcValue();
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int SVOffset = LD->getSrcValueOffset();
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MVT MemoryVT = LD->getMemoryVT();
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@@ -747,7 +744,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
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if (Input >= array_lengthof(Inputs)) {
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// The mask element does not index into any input vector.
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Ops.push_back(DAG.getNode(ISD::UNDEF, dl, IdxVT));
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Ops.push_back(DAG.getUNDEF(IdxVT));
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continue;
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}
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@@ -795,7 +792,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
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if (Input >= array_lengthof(Inputs)) {
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// The mask element is "undef" or indexes off the end of the input.
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Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
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Ops.push_back(DAG.getUNDEF(EltVT));
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continue;
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}
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@@ -811,7 +808,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
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Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, &Ops[0], Ops.size());
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} else if (InputUsed[0] == -1U) {
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// No input vectors were used! The result is undefined.
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Output = DAG.getNode(ISD::UNDEF, dl, NewVT);
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Output = DAG.getUNDEF(NewVT);
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} else {
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// At least one input vector was used. Create a new shuffle vector.
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SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
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@@ -820,7 +817,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
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SDValue Op0 = Inputs[InputUsed[0]];
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// If only one input was used, use an undefined vector for the other.
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SDValue Op1 = InputUsed[1] == -1U ?
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DAG.getNode(ISD::UNDEF, dl, NewVT) : Inputs[InputUsed[1]];
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DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
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Output = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, Op0, Op1, NewMask);
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}
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@@ -1075,7 +1072,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
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for (unsigned i = 0; i < MaskLength; ++i) {
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SDValue Arg = Mask.getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) {
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Ops[i] = DAG.getNode(ISD::UNDEF, dl, OpVT);
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Ops[i] = DAG.getUNDEF(OpVT);
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} else {
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uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
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Ops[i] = DAG.getConstant(Idx, OpVT);
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@@ -1219,7 +1216,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
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unsigned NumConcat = WidenNumElts/InVTNumElts;
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SmallVector<SDValue, 16> Ops(NumConcat);
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Ops[0] = InOp;
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
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SDValue UndefVal = DAG.getUNDEF(InVT);
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for (unsigned i = 1; i != NumConcat; ++i)
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Ops[i] = UndefVal;
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return DAG.getNode(Opcode, dl, WidenVT,
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@@ -1245,7 +1242,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
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DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
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DAG.getIntPtrConstant(i)));
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
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SDValue UndefVal = DAG.getUNDEF(EltVT);
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for (; i < WidenNumElts; ++i)
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Ops[i] = UndefVal;
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@@ -1337,7 +1334,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
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// and then widening it. To avoid this, we widen the input only if
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// it results in a legal type.
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SmallVector<SDValue, 16> Ops(NewNumElts);
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
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SDValue UndefVal = DAG.getUNDEF(InVT);
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Ops[0] = InOp;
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for (unsigned i = 1; i < NewNumElts; ++i)
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Ops[i] = UndefVal;
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@@ -1380,7 +1377,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
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SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
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NewOps.reserve(WidenNumElts);
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for (unsigned i = NumElts; i < WidenNumElts; ++i)
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NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
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NewOps.push_back(DAG.getUNDEF(EltVT));
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return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
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}
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@@ -1398,7 +1395,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
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// Add undef vectors to widen to correct length.
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unsigned NumConcat = WidenVT.getVectorNumElements() /
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InVT.getVectorNumElements();
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
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SDValue UndefVal = DAG.getUNDEF(InVT);
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SmallVector<SDValue, 16> Ops(NumConcat);
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for (unsigned i=0; i < NumOperands; ++i)
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Ops[i] = N->getOperand(i);
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@@ -1451,7 +1448,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
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Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
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DAG.getIntPtrConstant(j));
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}
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
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SDValue UndefVal = DAG.getUNDEF(EltVT);
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for (; Idx < WidenNumElts; ++Idx)
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Ops[Idx] = UndefVal;
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return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
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@@ -1495,7 +1492,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
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unsigned NumConcat = WidenNumElts/InVTNumElts;
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SmallVector<SDValue, 16> Ops(NumConcat);
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Ops[0] = InOp;
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
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SDValue UndefVal = DAG.getUNDEF(InVT);
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for (unsigned i = 1; i != NumConcat; ++i) {
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Ops[i] = UndefVal;
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}
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@@ -1528,7 +1525,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
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SatOp, CvtCode);
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}
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
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SDValue UndefVal = DAG.getUNDEF(EltVT);
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for (; i < WidenNumElts; ++i)
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Ops[i] = UndefVal;
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@@ -1582,7 +1579,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
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}
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}
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
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SDValue UndefVal = DAG.getUNDEF(EltVT);
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for (; i < WidenNumElts; ++i)
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Ops[i] = UndefVal;
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return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
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@@ -1638,7 +1635,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
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}
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// Fill the rest with undefs
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
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SDValue UndefVal = DAG.getUNDEF(EltVT);
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for (; i != WidenNumElts; ++i)
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Ops[i] = UndefVal;
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@@ -1706,7 +1703,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
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SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
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MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
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return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), WidenVT);
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return DAG.getUNDEF(WidenVT);
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}
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SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
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@@ -1737,7 +1734,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
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}
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}
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for (unsigned i = NumElts; i < WidenNumElts; ++i)
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MaskOps[i] = DAG.getNode(ISD::UNDEF, dl, IdxVT);
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MaskOps[i] = DAG.getUNDEF(IdxVT);
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SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
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MVT::getVectorVT(IdxVT, WidenNumElts),
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&MaskOps[0], WidenNumElts);
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@@ -2158,7 +2155,7 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
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if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
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unsigned NumConcat = WidenNumElts / InNumElts;
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SmallVector<SDValue, 16> Ops(NumConcat);
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
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SDValue UndefVal = DAG.getUNDEF(InVT);
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Ops[0] = InOp;
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for (unsigned i = 1; i != NumConcat; ++i)
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Ops[i] = UndefVal;
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@@ -2179,7 +2176,7 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
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Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
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DAG.getIntPtrConstant(Idx));
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
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SDValue UndefVal = DAG.getUNDEF(EltVT);
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for ( ; Idx < WidenNumElts; ++Idx)
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Ops[Idx] = UndefVal;
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return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);
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