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Changes to compile with GCC 2.96
Changes to support configurable pointer size and endianness git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5130 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -37,7 +37,7 @@ inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
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unsigned DestReg) {
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assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
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MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
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I = ++MBB->insert(I, MI);
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I = MBB->insert(I, MI)+1;
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return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
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}
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@ -49,7 +49,7 @@ inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
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unsigned NumOperands) {
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assert(I > MBB->begin() && I <= MBB->end() && "Bad iterator!");
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MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
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I = ++MBB->insert(I, MI);
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I = MBB->insert(I, MI)+1;
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return MachineInstrBuilder(MI);
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}
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@ -816,17 +816,43 @@ void ISel::visitShiftInst (ShiftInst &I) {
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/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
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/// instruction.
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/// instruction. The load and store instructions are the only place where we
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/// need to worry about the memory layout of the target machine.
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///
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void ISel::visitLoadInst(LoadInst &I) {
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bool isLittleEndian = TM.getTargetData().isLittleEndian();
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bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
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unsigned Class = getClass(I.getType());
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if (Class > 2) // FIXME: Handle longs and others...
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visitInstruction(I);
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static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
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unsigned SrcAddrReg = getReg(I.getOperand(0));
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unsigned AddressReg = getReg(I.getOperand(0));
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addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
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// We need to adjust the input pointer if we are emulating a big-endian
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// long-pointer target. On these systems, the pointer that we are interested
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// in is in the upper part of the eight byte memory image of the pointer. It
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// also happens to be byte-swapped, but this will be handled later.
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//
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if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getType())) {
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unsigned R = makeAnotherReg(Type::UIntTy);
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BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4);
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SrcAddrReg = R;
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}
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unsigned DestReg = getReg(I);
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unsigned IReg = DestReg;
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if (!isLittleEndian) { // If big endian we need an intermediate stage
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IReg = makeAnotherReg(I.getType());
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std::swap(IReg, DestReg);
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}
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addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
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if (!isLittleEndian) {
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// Emit the byte swap instruction...
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static const unsigned BSWAPOpcode[] = { X86::MOVrr8, X86::BSWAPr16, X86::BSWAPr32 };
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BuildMI(BB, BSWAPOpcode[Class], 1, IReg).addReg(DestReg);
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}
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}
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@ -834,6 +860,8 @@ void ISel::visitLoadInst(LoadInst &I) {
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/// instruction.
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///
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void ISel::visitStoreInst(StoreInst &I) {
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bool isLittleEndian = TM.getTargetData().isLittleEndian();
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bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
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unsigned Class = getClass(I.getOperand(0)->getType());
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if (Class > 2) // FIXME: Handle longs and others...
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visitInstruction(I);
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@ -842,6 +870,21 @@ void ISel::visitStoreInst(StoreInst &I) {
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unsigned ValReg = getReg(I.getOperand(0));
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unsigned AddressReg = getReg(I.getOperand(1));
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if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getOperand(0)->getType())) {
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unsigned R = makeAnotherReg(Type::UIntTy);
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BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4);
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AddressReg = R;
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}
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if (!isLittleEndian && Class) {
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// Emit the byte swap instruction...
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static const unsigned BSWAPOpcode[] = { X86::MOVrr8, X86::BSWAPr16, X86::BSWAPr32 };
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unsigned R = makeAnotherReg(I.getOperand(0)->getType());
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BuildMI(BB, BSWAPOpcode[Class], 1, R).addReg(ValReg);
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ValReg = R;
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}
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addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
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}
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@ -983,7 +1026,7 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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// be constant, we can get its value and use it to find the
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// right byte offset from the StructLayout class's list of
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// structure member offsets.
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unsigned idxValue = CUI->getValue ();
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unsigned idxValue = CUI->getValue();
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unsigned memberOffset =
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TD.getStructLayout (StTy)->MemberOffsets[idxValue];
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// Emit an ADD to add memberOffset to the basePtr.
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@ -37,7 +37,7 @@ inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
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unsigned DestReg) {
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assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
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MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
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I = ++MBB->insert(I, MI);
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I = MBB->insert(I, MI)+1;
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return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
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}
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@ -49,7 +49,7 @@ inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
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unsigned NumOperands) {
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assert(I > MBB->begin() && I <= MBB->end() && "Bad iterator!");
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MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
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I = ++MBB->insert(I, MI);
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I = MBB->insert(I, MI)+1;
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return MachineInstrBuilder(MI);
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}
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@ -816,17 +816,43 @@ void ISel::visitShiftInst (ShiftInst &I) {
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/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
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/// instruction.
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/// instruction. The load and store instructions are the only place where we
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/// need to worry about the memory layout of the target machine.
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///
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void ISel::visitLoadInst(LoadInst &I) {
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bool isLittleEndian = TM.getTargetData().isLittleEndian();
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bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
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unsigned Class = getClass(I.getType());
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if (Class > 2) // FIXME: Handle longs and others...
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visitInstruction(I);
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static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
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unsigned SrcAddrReg = getReg(I.getOperand(0));
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unsigned AddressReg = getReg(I.getOperand(0));
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addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
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// We need to adjust the input pointer if we are emulating a big-endian
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// long-pointer target. On these systems, the pointer that we are interested
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// in is in the upper part of the eight byte memory image of the pointer. It
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// also happens to be byte-swapped, but this will be handled later.
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//
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if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getType())) {
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unsigned R = makeAnotherReg(Type::UIntTy);
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BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4);
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SrcAddrReg = R;
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}
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unsigned DestReg = getReg(I);
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unsigned IReg = DestReg;
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if (!isLittleEndian) { // If big endian we need an intermediate stage
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IReg = makeAnotherReg(I.getType());
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std::swap(IReg, DestReg);
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}
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addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
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if (!isLittleEndian) {
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// Emit the byte swap instruction...
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static const unsigned BSWAPOpcode[] = { X86::MOVrr8, X86::BSWAPr16, X86::BSWAPr32 };
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BuildMI(BB, BSWAPOpcode[Class], 1, IReg).addReg(DestReg);
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}
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}
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@ -834,6 +860,8 @@ void ISel::visitLoadInst(LoadInst &I) {
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/// instruction.
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///
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void ISel::visitStoreInst(StoreInst &I) {
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bool isLittleEndian = TM.getTargetData().isLittleEndian();
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bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
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unsigned Class = getClass(I.getOperand(0)->getType());
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if (Class > 2) // FIXME: Handle longs and others...
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visitInstruction(I);
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@ -842,6 +870,21 @@ void ISel::visitStoreInst(StoreInst &I) {
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unsigned ValReg = getReg(I.getOperand(0));
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unsigned AddressReg = getReg(I.getOperand(1));
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if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getOperand(0)->getType())) {
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unsigned R = makeAnotherReg(Type::UIntTy);
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BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4);
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AddressReg = R;
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}
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if (!isLittleEndian && Class) {
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// Emit the byte swap instruction...
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static const unsigned BSWAPOpcode[] = { X86::MOVrr8, X86::BSWAPr16, X86::BSWAPr32 };
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unsigned R = makeAnotherReg(I.getOperand(0)->getType());
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BuildMI(BB, BSWAPOpcode[Class], 1, R).addReg(ValReg);
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ValReg = R;
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}
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addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
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}
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@ -983,7 +1026,7 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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// be constant, we can get its value and use it to find the
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// right byte offset from the StructLayout class's list of
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// structure member offsets.
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unsigned idxValue = CUI->getValue ();
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unsigned idxValue = CUI->getValue();
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unsigned memberOffset =
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TD.getStructLayout (StTy)->MemberOffsets[idxValue];
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// Emit an ADD to add memberOffset to the basePtr.
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