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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-02 11:30:10 +00:00
Reapply considered harmfull part of rr112934 and r112942.
"Use target specific nodes instead of relying in unpckl and unpckh pattern fragments during isel time. Also place a depth limit in getShuffleScalarElt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113020 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
ee72651df4
commit
e8f279cbd4
@ -16,6 +16,7 @@
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86ISelLowering.h"
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#include "X86ShuffleDecode.h"
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#include "X86TargetMachine.h"
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#include "X86TargetObjectFile.h"
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#include "llvm/CallingConv.h"
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@ -3687,7 +3688,11 @@ static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
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/// getShuffleScalarElt - Returns the scalar element that will make up the ith
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/// element of the result of the vector shuffle.
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SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG) {
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SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
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unsigned Depth) {
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if (Depth == 6)
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return SDValue(); // Limit search depth.
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SDValue V = SDValue(N, 0);
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EVT VT = V.getValueType();
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unsigned Opcode = V.getOpcode();
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@ -3701,24 +3706,86 @@ SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG) {
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int NumElems = VT.getVectorNumElements();
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SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
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return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG);
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return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
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}
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// Recurse into target specific vector shuffles to find scalars.
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if (isTargetShuffle(Opcode)) {
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int NumElems = VT.getVectorNumElements();
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SmallVector<unsigned, 16> ShuffleMask;
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SDValue ImmN;
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switch(Opcode) {
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case X86ISD::SHUFPS:
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case X86ISD::SHUFPD:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodeSHUFPSMask(NumElems,
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cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::PUNPCKHBW:
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case X86ISD::PUNPCKHWD:
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case X86ISD::PUNPCKHDQ:
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case X86ISD::PUNPCKHQDQ:
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DecodePUNPCKHMask(NumElems, ShuffleMask);
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break;
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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DecodeUNPCKHPMask(NumElems, ShuffleMask);
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break;
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case X86ISD::PUNPCKLBW:
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case X86ISD::PUNPCKLWD:
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case X86ISD::PUNPCKLDQ:
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case X86ISD::PUNPCKLQDQ:
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DecodePUNPCKLMask(NumElems, ShuffleMask);
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break;
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case X86ISD::UNPCKLPS:
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case X86ISD::UNPCKLPD:
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DecodeUNPCKLPMask(NumElems, ShuffleMask);
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break;
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case X86ISD::MOVHLPS:
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DecodeMOVHLPSMask(NumElems, ShuffleMask);
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break;
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case X86ISD::MOVLHPS:
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DecodeMOVLHPSMask(NumElems, ShuffleMask);
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break;
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case X86ISD::PSHUFD:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodePSHUFMask(NumElems,
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cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::PSHUFHW:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::PSHUFLW:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::MOVSS:
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case X86ISD::MOVSD: {
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// The index 0 always comes from the first element of the second source,
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// this is why MOVSS and MOVSD are used in the first place. The other
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// elements come from the other positions of the first source vector.
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unsigned OpNum = (Index == 0) ? 1 : 0;
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return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG);
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return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
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Depth+1);
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}
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default:
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assert("not implemented for target shuffle node");
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return SDValue();
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}
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Index = ShuffleMask[Index];
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if (Index < 0)
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return DAG.getUNDEF(VT.getVectorElementType());
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SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
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return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
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Depth+1);
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}
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// Actual nodes that may contain scalar elements
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@ -3751,7 +3818,7 @@ unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
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while (i < NumElems) {
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unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
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SDValue Elt = getShuffleScalarElt(N, Index, DAG);
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SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
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if (!(Elt.getNode() &&
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(Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
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break;
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@ -5364,9 +5431,13 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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return getMOVL(DAG, dl, VT, V2, V1);
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}
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if (X86::isUNPCKLMask(SVOp) ||
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X86::isUNPCKHMask(SVOp))
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return Op;
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if (X86::isUNPCKLMask(SVOp))
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return (isMMX) ?
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Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
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if (X86::isUNPCKHMask(SVOp))
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return (isMMX) ?
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Op : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
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if (V2IsSplat) {
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// Normalize mask so all entries that point to V2 points to its first
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@ -5388,9 +5459,14 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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// FIXME: this seems wrong.
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SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
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ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
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if (X86::isUNPCKLMask(NewSVOp) ||
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X86::isUNPCKHMask(NewSVOp))
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return NewOp;
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if (X86::isUNPCKLMask(NewSVOp))
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return (isMMX) ?
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NewOp : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
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if (X86::isUNPCKHMask(NewSVOp))
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return (isMMX) ?
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NewOp : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
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}
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// FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
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@ -9731,7 +9807,7 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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SmallVector<SDValue, 16> Elts;
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for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
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Elts.push_back(getShuffleScalarElt(N, i, DAG));
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Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
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return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
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}
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@ -10659,7 +10735,6 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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SelectionDAG &DAG = DCI.DAG;
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switch (N->getOpcode()) {
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default: break;
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case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
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case ISD::EXTRACT_VECTOR_ELT:
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return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
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case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
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@ -10676,6 +10751,28 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
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case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
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case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
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case X86ISD::SHUFPS: // Handle all target specific shuffles
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case X86ISD::SHUFPD:
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case X86ISD::PUNPCKHBW:
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case X86ISD::PUNPCKHWD:
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case X86ISD::PUNPCKHDQ:
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case X86ISD::PUNPCKHQDQ:
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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case X86ISD::PUNPCKLBW:
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case X86ISD::PUNPCKLWD:
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case X86ISD::PUNPCKLDQ:
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case X86ISD::PUNPCKLQDQ:
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case X86ISD::UNPCKLPS:
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case X86ISD::UNPCKLPD:
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case X86ISD::MOVHLPS:
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case X86ISD::MOVLHPS:
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case X86ISD::PSHUFD:
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case X86ISD::PSHUFHW:
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case X86ISD::PSHUFLW:
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case X86ISD::MOVSS:
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case X86ISD::MOVSD:
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case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
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}
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return SDValue();
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