diff --git a/include/llvm/IntrinsicsXCore.td b/include/llvm/IntrinsicsXCore.td
index 96e2896a3cc..e633af045c3 100644
--- a/include/llvm/IntrinsicsXCore.td
+++ b/include/llvm/IntrinsicsXCore.td
@@ -69,4 +69,21 @@ let TargetPrefix = "xcore" in {  // All intrinsics start with "llvm.xcore.".
   def int_xcore_checkevent : Intrinsic<[llvm_ptr_ty],[llvm_ptr_ty]>;
 
   def int_xcore_clre : Intrinsic<[],[],[]>;
+
+  // Intrinsics for threads.
+  def int_xcore_getst : Intrinsic <[llvm_anyptr_ty],[llvm_anyptr_ty],
+                                   [NoCapture<0>]>;
+  def int_xcore_msync : Intrinsic <[],[llvm_anyptr_ty], [NoCapture<0>]>;
+  def int_xcore_ssync : Intrinsic <[],[]>;
+  def int_xcore_mjoin : Intrinsic <[],[llvm_anyptr_ty], [NoCapture<0>]>;
+  def int_xcore_initsp : Intrinsic <[],[llvm_anyptr_ty, llvm_ptr_ty],
+                                    [NoCapture<0>]>;
+  def int_xcore_initpc : Intrinsic <[],[llvm_anyptr_ty, llvm_ptr_ty],
+                                    [NoCapture<0>]>;
+  def int_xcore_initlr : Intrinsic <[],[llvm_anyptr_ty, llvm_ptr_ty],
+                                    [NoCapture<0>]>;
+  def int_xcore_initcp : Intrinsic <[],[llvm_anyptr_ty, llvm_ptr_ty],
+                                    [NoCapture<0>]>;
+  def int_xcore_initdp : Intrinsic <[],[llvm_anyptr_ty, llvm_ptr_ty],
+                                    [NoCapture<0>]>;
 }
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index 67be13866a6..789546ed304 100644
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -739,7 +739,7 @@ def BL_lu10 : _FLU10<
 }
 
 // Two operand short
-// TODO getr, getst
+// TODO eet, eef, testwct, tsetmr, sext (reg), zext (reg)
 def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
                  "not $dst, $b",
                  [(set GRRegs:$dst, (not GRRegs:$b))]>;
@@ -748,8 +748,6 @@ def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
                  "neg $dst, $b",
                  [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
 
-// TODO setd, eet, eef, testwct, tinitpc, tinitdp,
-// tinitsp, tinitcp, tsetmr, sext (reg), zext (reg)
 let Constraints = "$src1 = $dst" in {
 let neverHasSideEffects = 1 in
 def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
@@ -837,9 +835,29 @@ def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
                  "setd res[$r], $val",
                  [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
 
+def GETST_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
+                    "getst $dst, res[$r]",
+                    [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
+
+def INITSP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
+                     "init t[$t]:sp, $src",
+                     [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
+
+def INITPC_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
+                     "init t[$t]:pc, $src",
+                     [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
+
+def INITCP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
+                     "init t[$t]:cp, $src",
+                     [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
+
+def INITDP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
+                     "init t[$t]:dp, $src",
+                     [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
+
 // Two operand long
 // TODO endin, peek,
-// getd, testlcl, tinitlr
+// getd, testlcl
 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
                  "bitrev $dst, $src",
                  [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
@@ -868,6 +886,10 @@ def SETPS_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
                  "set ps[$src1], $src2",
                  [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
 
+def INITLR_l2r : _FL2R<(outs), (ins GRRegs:$t, GRRegs:$src),
+                       "init t[$t]:lr, $src",
+                       [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
+
 def SETCLK_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
                        "setclk res[$src1], $src2",
                        [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
@@ -881,9 +903,16 @@ def SETPSC_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
                        [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
 
 // One operand short
-// TODO edu, eeu, waitet, waitef, tstart, msync, mjoin, clrtp
+// TODO edu, eeu, waitet, waitef, tstart, clrtp
 // setdp, setcp, setev, kcall
 // dgetreg
+def MSYNC_1r : _F1R<(outs), (ins GRRegs:$i),
+                    "msync res[$i]",
+		    [(int_xcore_msync GRRegs:$i)]>;
+def MJOIN_1r : _F1R<(outs), (ins GRRegs:$i),
+                    "mjoin res[$i]",
+		    [(int_xcore_mjoin GRRegs:$i)]>;
+
 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
 def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
                  "bau $addr",
@@ -940,7 +969,7 @@ def EEU_1r : _F1R<(outs), (ins GRRegs:$r),
                [(int_xcore_eeu GRRegs:$r)]>;
 
 // Zero operand short
-// TODO ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
+// TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
 // stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
 // dentsp, drestsp
 
@@ -951,6 +980,10 @@ def GETID_0R : _F0R<(outs), (ins),
                  "get r11, id",
                  [(set R11, (int_xcore_getid))]>;
 
+def SSYNC_0r : _F0R<(outs), (ins),
+                    "ssync",
+		    [(int_xcore_ssync)]>;
+
 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
     hasSideEffects = 1 in
 def WAITEU_0R : _F0R<(outs), (ins),
diff --git a/test/CodeGen/XCore/threads.ll b/test/CodeGen/XCore/threads.ll
new file mode 100644
index 00000000000..a0558e365cb
--- /dev/null
+++ b/test/CodeGen/XCore/threads.ll
@@ -0,0 +1,67 @@
+; RUN: llc -march=xcore < %s | FileCheck %s
+
+declare i8 addrspace(1)* @llvm.xcore.getst.p1i8.p1i8(i8 addrspace(1)* %r)
+declare void @llvm.xcore.msync.p1i8(i8 addrspace(1)* %r)
+declare void @llvm.xcore.ssync()
+declare void @llvm.xcore.mjoin.p1i8(i8 addrspace(1)* %r)
+declare void @llvm.xcore.initsp.p1i8(i8 addrspace(1)* %r, i8* %value)
+declare void @llvm.xcore.initpc.p1i8(i8 addrspace(1)* %r, i8* %value)
+declare void @llvm.xcore.initlr.p1i8(i8 addrspace(1)* %r, i8* %value)
+declare void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %r, i8* %value)
+declare void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %r, i8* %value)
+
+define i8 addrspace(1)* @getst(i8 addrspace(1)* %r) {
+; CHECK: getst:
+; CHECK: getst r0, res[r0]
+        %result = call i8 addrspace(1)* @llvm.xcore.getst.p1i8.p1i8(i8 addrspace(1)* %r)
+        ret i8 addrspace(1)* %result
+}
+
+define void @ssync() {
+; CHECK: ssync:
+; CHECK: ssync
+	call void @llvm.xcore.ssync()
+	ret void
+}
+
+define void @mjoin(i8 addrspace(1)* %r) {
+; CHECK: mjoin:
+; CHECK: mjoin res[r0]
+	call void @llvm.xcore.mjoin.p1i8(i8 addrspace(1)* %r)
+	ret void
+}
+
+define void @initsp(i8 addrspace(1)* %t, i8* %src) {
+; CHECK: initsp:
+; CHECK: init t[r0]:sp, r1
+        call void @llvm.xcore.initsp.p1i8(i8 addrspace(1)* %t, i8* %src)
+        ret void
+}
+
+define void @initpc(i8 addrspace(1)* %t, i8* %src) {
+; CHECK: initpc:
+; CHECK: init t[r0]:pc, r1
+        call void @llvm.xcore.initpc.p1i8(i8 addrspace(1)* %t, i8* %src)
+        ret void
+}
+
+define void @initlr(i8 addrspace(1)* %t, i8* %src) {
+; CHECK: initlr:
+; CHECK: init t[r0]:lr, r1
+        call void @llvm.xcore.initlr.p1i8(i8 addrspace(1)* %t, i8* %src)
+        ret void
+}
+
+define void @initcp(i8 addrspace(1)* %t, i8* %src) {
+; CHECK: initcp:
+; CHECK: init t[r0]:cp, r1
+        call void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %t, i8* %src)
+        ret void
+}
+
+define void @initdp(i8 addrspace(1)* %t, i8* %src) {
+; CHECK: initdp:
+; CHECK: init t[r0]:dp, r1
+        call void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %t, i8* %src)
+        ret void
+}