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* OK, after changing to use liveIn/liveOut instead of IDEFs,
to avoid redundant mov out3=r44 type instructions, we need to tell the register allocator the truth about out? registers. FIXME: unfortunately, since the list of allocatable registers is immutable, we can't simply 'delete r127' from the allocation order, say, if 'out0' is used. The only correct thing we can do is have a linear order of regs: out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127 and slide a 'window' of 96 registers along this line, depending on how many of the out? regs a function actually uses. The only downside of this is that the out? registers will be allocated _first_, which makes the resulting assembly ugly. :( Note this in the README. Hope this gets fixed soon. :) (note the 3rd person speech there) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21252 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -234,7 +234,13 @@ def B6 : GR<0, "b6">;
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// in IA64RegisterInfo.cpp
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// in IA64RegisterInfo.cpp
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def GR : RegisterClass<i64, 64,
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def GR : RegisterClass<i64, 64,
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[r3, r8, r9, r10, r11, r14,
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[
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//FIXME!: for readability, we don't want the out registers to be the first
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// ones allocated
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out7, out6, out5, out4, out3, out2, out1, out0,
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r3, r8, r9, r10, r11, r14,
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r16, r17, r18, r19, r20, r21, r23,
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r16, r17, r18, r19, r20, r21, r23,
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r24, r25, r26, r27, r28, r29, r30, r31,
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r24, r25, r26, r27, r28, r29, r30, r31,
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r32, r33, r34, r35, r36, r37, r38, r39,
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r32, r33, r34, r35, r36, r37, r38, r39,
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@ -249,13 +255,18 @@ def GR : RegisterClass<i64, 64,
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r104, r105, r106, r107, r108, r109, r110, r111,
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r104, r105, r106, r107, r108, r109, r110, r111,
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r112, r113, r114, r115, r116, r117, r118, r119,
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r112, r113, r114, r115, r116, r117, r118, r119,
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r120, r121, r122, r123, r124, r125, r126, r127,
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r120, r121, r122, r123, r124, r125, r126, r127,
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out0, out1, out2, out3,
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r0, r1, r2, r12, r13, r15, r22]> // the last 15 are special (look down)
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out4, out5, out6, out7,
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r0, r1, r2, r12, r13, r15, r22]> // these last 7 are special (look down)
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{
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{
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let Methods = [{
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let Methods = [{
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iterator allocation_order_begin(MachineFunction &MF) const {
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// hide registers appropriately:
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return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
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}
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iterator allocation_order_end(MachineFunction &MF) const {
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iterator allocation_order_end(MachineFunction &MF) const {
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int numReservedRegs=7; // the 15 special registers r0,r1,r2,r12,r13 etc
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int numReservedRegs=7; // the 7 special registers r0,r1,r2,r12,r13 etc
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// we also can't allocate registers for use as locals if they're
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// we also can't allocate registers for use as locals if they're
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// already required as 'out' registers
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// already required as 'out' registers
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numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
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numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
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@ -55,6 +55,8 @@ I guarantee it.
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TODO:
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TODO:
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- clean up and thoroughly test the isel patterns.
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- clean up and thoroughly test the isel patterns.
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- fix stacked register allocation order: (for readability) we don't want
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the out? registers being the first ones used
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- fix up floating point
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- fix up floating point
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(nb http://gcc.gnu.org/wiki?pagename=ia64%20floating%20point )
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(nb http://gcc.gnu.org/wiki?pagename=ia64%20floating%20point )
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- bundling!
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- bundling!
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