mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
AArch64/ARM64: enable directcond.ll test on ARM64.
Code change is because optimizeCompareInstr didn't know how to pull the condition code out of FCSEL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206171 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
97c1fc0832
commit
e90d4e2c69
@ -775,6 +775,8 @@ bool ARM64InstrInfo::optimizeCompareInstr(
|
||||
case ARM64::CSELXr:
|
||||
case ARM64::CSNEGWr:
|
||||
case ARM64::CSNEGXr:
|
||||
case ARM64::FCSELSrrr:
|
||||
case ARM64::FCSELDrrr:
|
||||
CC = (ARM64CC::CondCode)Instr.getOperand(IO - 1).getImm();
|
||||
break;
|
||||
}
|
||||
|
@ -1,11 +1,13 @@
|
||||
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
||||
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
|
||||
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
|
||||
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
|
||||
|
||||
define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test_select_i32:
|
||||
%val = select i1 %bit, i32 %a, i32 %b
|
||||
; CHECK: movz [[ONE:w[0-9]+]], #1
|
||||
; CHECK: tst w0, [[ONE]]
|
||||
; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
|
||||
; CHECK-AARCH64: tst w0, [[ONE]]
|
||||
; CHECK-ARM64: tst w0, #0x1
|
||||
; CHECK-NEXT: csel w0, w1, w2, ne
|
||||
|
||||
ret i32 %val
|
||||
@ -14,8 +16,9 @@ define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
|
||||
define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_select_i64:
|
||||
%val = select i1 %bit, i64 %a, i64 %b
|
||||
; CHECK: movz [[ONE:w[0-9]+]], #1
|
||||
; CHECK: tst w0, [[ONE]]
|
||||
; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
|
||||
; CHECK-AARCH64: tst w0, [[ONE]]
|
||||
; CHECK-ARM64: tst w0, #0x1
|
||||
; CHECK-NEXT: csel x0, x1, x2, ne
|
||||
|
||||
ret i64 %val
|
||||
@ -24,8 +27,9 @@ define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
|
||||
define float @test_select_float(i1 %bit, float %a, float %b) {
|
||||
; CHECK-LABEL: test_select_float:
|
||||
%val = select i1 %bit, float %a, float %b
|
||||
; CHECK: movz [[ONE:w[0-9]+]], #1
|
||||
; CHECK: tst w0, [[ONE]]
|
||||
; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
|
||||
; CHECK-AARCH64: tst w0, [[ONE]]
|
||||
; CHECK-ARM64: tst w0, #0x1
|
||||
; CHECK-NEXT: fcsel s0, s0, s1, ne
|
||||
; CHECK-NOFP-NOT: fcsel
|
||||
ret float %val
|
||||
@ -34,8 +38,9 @@ define float @test_select_float(i1 %bit, float %a, float %b) {
|
||||
define double @test_select_double(i1 %bit, double %a, double %b) {
|
||||
; CHECK-LABEL: test_select_double:
|
||||
%val = select i1 %bit, double %a, double %b
|
||||
; CHECK: movz [[ONE:w[0-9]+]], #1
|
||||
; CHECK: tst w0, [[ONE]]
|
||||
; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
|
||||
; CHECK-AARCH64: tst w0, [[ONE]]
|
||||
; CHECK-ARM64: tst w0, #0x1
|
||||
; CHECK-NEXT: fcsel d0, d0, d1, ne
|
||||
; CHECK-NOFP-NOT: fcsel
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user