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R600: Rely on TypeLegalizer to use divrem instead of div/rem

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reviewer: tstellardAMD

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238337 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jan Vesely 2015-05-27 16:54:10 +00:00
parent 72be0e4224
commit e93c0d6817
1 changed files with 0 additions and 43 deletions
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43
lib/Target/R600/R600ISelLowering.cpp
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@ -171,13 +171,6 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM,
setTargetDAGCombine(ISD::SELECT_CC);
setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
// These should be replaced by UDVIREM, but it does not happen automatically
// during Type Legalization
setOperationAction(ISD::UDIV, MVT::i64, Custom);
setOperationAction(ISD::UREM, MVT::i64, Custom);
setOperationAction(ISD::SDIV, MVT::i64, Custom);
setOperationAction(ISD::SREM, MVT::i64, Custom);
// We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
// to be Legal/Custom in order to avoid library calls.
setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
@ -879,42 +872,6 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(Result);
return;
}
case ISD::UDIV: {
SDValue Op = SDValue(N, 0);
SDLoc DL(Op);
EVT VT = Op.getValueType();
SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
N->getOperand(0), N->getOperand(1));
Results.push_back(UDIVREM);
break;
}
case ISD::UREM: {
SDValue Op = SDValue(N, 0);
SDLoc DL(Op);
EVT VT = Op.getValueType();
SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
N->getOperand(0), N->getOperand(1));
Results.push_back(UDIVREM.getValue(1));
break;
}
case ISD::SDIV: {
SDValue Op = SDValue(N, 0);
SDLoc DL(Op);
EVT VT = Op.getValueType();
SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
N->getOperand(0), N->getOperand(1));
Results.push_back(SDIVREM);
break;
}
case ISD::SREM: {
SDValue Op = SDValue(N, 0);
SDLoc DL(Op);
EVT VT = Op.getValueType();
SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
N->getOperand(0), N->getOperand(1));
Results.push_back(SDIVREM.getValue(1));
break;
}
case ISD::SDIVREM: {
SDValue Op = SDValue(N, 1);
SDValue RES = LowerSDIVREM(Op, DAG);