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Fix PR7748 without using microsoft extensions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112128 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-08-26 01:02:53 +00:00
parent ae47c6d69e
commit e943c15621
2 changed files with 13 additions and 13 deletions
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12
lib/Target/X86/X86InstrInfo.h
View File

@ -445,27 +445,27 @@ namespace X86II {
//===------------------------------------------------------------------===// //===------------------------------------------------------------------===//
// VEX - The opcode prefix used by AVX instructions // VEX - The opcode prefix used by AVX instructions
VEX = 1ULL << 32, VEX = 1U << 0,
// VEX_W - Has a opcode specific functionality, but is used in the same // VEX_W - Has a opcode specific functionality, but is used in the same
// way as REX_W is for regular SSE instructions. // way as REX_W is for regular SSE instructions.
VEX_W = 1ULL << 33, VEX_W = 1U << 1,
// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 // VEX_4V - Used to specify an additional AVX/SSE register. Several 2
// address instructions in SSE are represented as 3 address ones in AVX // address instructions in SSE are represented as 3 address ones in AVX
// and the additional register is encoded in VEX_VVVV prefix. // and the additional register is encoded in VEX_VVVV prefix.
VEX_4V = 1ULL << 34, VEX_4V = 1U << 2,
// VEX_I8IMM - Specifies that the last register used in a AVX instruction, // VEX_I8IMM - Specifies that the last register used in a AVX instruction,
// must be encoded in the i8 immediate field. This usually happens in // must be encoded in the i8 immediate field. This usually happens in
// instructions with 4 operands. // instructions with 4 operands.
VEX_I8IMM = 1ULL << 35, VEX_I8IMM = 1U << 3,
// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current // VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
// instruction uses 256-bit wide registers. This is usually auto detected if // instruction uses 256-bit wide registers. This is usually auto detected if
// a VR256 register is used, but some AVX instructions also have this field // a VR256 register is used, but some AVX instructions also have this field
// marked when using a f256 memory references. // marked when using a f256 memory references.
VEX_L = 1ULL << 36 VEX_L = 1U << 4
}; };
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
@ -533,7 +533,7 @@ namespace X86II {
case X86II::MRMDestMem: case X86II::MRMDestMem:
return 0; return 0;
case X86II::MRMSrcMem: { case X86II::MRMSrcMem: {
bool HasVEX_4V = TSFlags & X86II::VEX_4V; bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V;
unsigned FirstMemOp = 1; unsigned FirstMemOp = 1;
if (HasVEX_4V) if (HasVEX_4V)
++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).

14
lib/Target/X86/X86MCCodeEmitter.cpp
View File

@ -365,7 +365,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
const TargetInstrDesc &Desc, const TargetInstrDesc &Desc,
raw_ostream &OS) const { raw_ostream &OS) const {
bool HasVEX_4V = false; bool HasVEX_4V = false;
if (TSFlags & X86II::VEX_4V) if ((TSFlags >> 32) & X86II::VEX_4V)
HasVEX_4V = true; HasVEX_4V = true;
// VEX_R: opcode externsion equivalent to REX.R in // VEX_R: opcode externsion equivalent to REX.R in
@ -429,10 +429,10 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
if (TSFlags & X86II::OpSize) if (TSFlags & X86II::OpSize)
VEX_PP = 0x01; VEX_PP = 0x01;
if (TSFlags & X86II::VEX_W) if ((TSFlags >> 32) & X86II::VEX_W)
VEX_W = 1; VEX_W = 1;
if (TSFlags & X86II::VEX_L) if ((TSFlags >> 32) & X86II::VEX_L)
VEX_L = 1; VEX_L = 1;
switch (TSFlags & X86II::Op0Mask) { switch (TSFlags & X86II::Op0Mask) {
@ -501,7 +501,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
// If the last register should be encoded in the immediate field // If the last register should be encoded in the immediate field
// do not use any bit from VEX prefix to this register, ignore it // do not use any bit from VEX prefix to this register, ignore it
if (TSFlags & X86II::VEX_I8IMM) if ((TSFlags >> 32) & X86II::VEX_I8IMM)
NumOps--; NumOps--;
for (; CurOp != NumOps; ++CurOp) { for (; CurOp != NumOps; ++CurOp) {
@ -801,9 +801,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
// It uses the VEX.VVVV field? // It uses the VEX.VVVV field?
bool HasVEX_4V = false; bool HasVEX_4V = false;
if (TSFlags & X86II::VEX) if ((TSFlags >> 32) & X86II::VEX)
HasVEXPrefix = true; HasVEXPrefix = true;
if (TSFlags & X86II::VEX_4V) if ((TSFlags >> 32) & X86II::VEX_4V)
HasVEX_4V = true; HasVEX_4V = true;
// Determine where the memory operand starts, if present. // Determine where the memory operand starts, if present.
@ -955,7 +955,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
if (CurOp != NumOps) { if (CurOp != NumOps) {
// The last source register of a 4 operand instruction in AVX is encoded // The last source register of a 4 operand instruction in AVX is encoded
// in bits[7:4] of a immediate byte, and bits[3:0] are ignored. // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
if (TSFlags & X86II::VEX_I8IMM) { if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
const MCOperand &MO = MI.getOperand(CurOp++); const MCOperand &MO = MI.getOperand(CurOp++);
bool IsExtReg = bool IsExtReg =
X86InstrInfo::isX86_64ExtendedReg(MO.getReg()); X86InstrInfo::isX86_64ExtendedReg(MO.getReg());