mirror of
https://github.com/c64scene-ar/llvm-6502.git
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NEON VLD4(one lane) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
10c6fdcd11
commit
e983a134e7
@ -306,6 +306,57 @@ def VecListThreeQWordIndexed : Operand<i32> {
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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// Register list of four D registers with byte lane subscripting.
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def VecListFourDByteIndexAsmOperand : AsmOperandClass {
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let Name = "VecListFourDByteIndexed";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListIndexedOperands";
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}
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def VecListFourDByteIndexed : Operand<i32> {
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let ParserMatchClass = VecListFourDByteIndexAsmOperand;
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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// ...with half-word lane subscripting.
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def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
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let Name = "VecListFourDHWordIndexed";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListIndexedOperands";
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}
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def VecListFourDHWordIndexed : Operand<i32> {
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let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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// ...with word lane subscripting.
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def VecListFourDWordIndexAsmOperand : AsmOperandClass {
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let Name = "VecListFourDWordIndexed";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListIndexedOperands";
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}
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def VecListFourDWordIndexed : Operand<i32> {
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let ParserMatchClass = VecListFourDWordIndexAsmOperand;
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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// Register list of four Q registers with half-word lane subscripting.
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def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
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let Name = "VecListFourQHWordIndexed";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListIndexedOperands";
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}
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def VecListFourQHWordIndexed : Operand<i32> {
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let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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// ...with word lane subscripting.
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def VecListFourQWordIndexAsmOperand : AsmOperandClass {
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let Name = "VecListFourQWordIndexed";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListIndexedOperands";
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}
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def VecListFourQWordIndexed : Operand<i32> {
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let ParserMatchClass = VecListFourQWordIndexAsmOperand;
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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//===----------------------------------------------------------------------===//
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// NEON-specific DAG Nodes.
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@ -6203,6 +6254,55 @@ def VST3qWB_register_Asm_32 :
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(ins VecListThreeQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VLD4 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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(ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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(ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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(ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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(ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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(ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNdWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
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(ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNdWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
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(ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNdWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
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(ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNqWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
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(ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNqWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
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(ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VLD4LNdWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
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(ins VecListFourDByteIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4LNdWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
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(ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4LNdWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
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(ins VecListFourDWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4LNqWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
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(ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4LNqWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
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(ins VecListFourQWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VLD4 multiple structure pseudo-instructions. These need special handling for
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@ -1203,6 +1203,31 @@ public:
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return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
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}
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bool isVecListFourDByteIndexed() const {
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if (!isSingleSpacedVectorIndexed()) return false;
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return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
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}
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bool isVecListFourDHWordIndexed() const {
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if (!isSingleSpacedVectorIndexed()) return false;
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return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
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}
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bool isVecListFourQWordIndexed() const {
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if (!isDoubleSpacedVectorIndexed()) return false;
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return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
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}
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bool isVecListFourQHWordIndexed() const {
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if (!isDoubleSpacedVectorIndexed()) return false;
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return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
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}
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bool isVecListFourDWordIndexed() const {
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if (!isSingleSpacedVectorIndexed()) return false;
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return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
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}
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bool isVectorIndex8() const {
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if (Kind != k_VectorIndex) return false;
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return VectorIndex.Val < 8;
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@ -5338,6 +5363,23 @@ static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
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case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
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case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
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// VLD4LN
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case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
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case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
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case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
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case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
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case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
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case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
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case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
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case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
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case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
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case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
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case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
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case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
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case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
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case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
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case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
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// VLD4
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case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
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case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
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@ -5665,6 +5707,41 @@ processInstruction(MCInst &Inst,
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return true;
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}
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case ARM::VLD4LNdWB_register_Asm_8:
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case ARM::VLD4LNdWB_register_Asm_16:
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case ARM::VLD4LNdWB_register_Asm_32:
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case ARM::VLD4LNqWB_register_Asm_16:
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case ARM::VLD4LNqWB_register_Asm_32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(Inst.getOperand(4)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(5)); // CondCode
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TmpInst.addOperand(Inst.getOperand(6));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD1LNdWB_fixed_Asm_8:
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case ARM::VLD1LNdWB_fixed_Asm_16:
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case ARM::VLD1LNdWB_fixed_Asm_32: {
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@ -5744,6 +5821,41 @@ processInstruction(MCInst &Inst,
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return true;
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}
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case ARM::VLD4LNdWB_fixed_Asm_8:
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case ARM::VLD4LNdWB_fixed_Asm_16:
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case ARM::VLD4LNdWB_fixed_Asm_32:
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case ARM::VLD4LNqWB_fixed_Asm_16:
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case ARM::VLD4LNqWB_fixed_Asm_32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD1LNdAsm_8:
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case ARM::VLD1LNdAsm_16:
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case ARM::VLD1LNdAsm_32: {
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@ -5817,6 +5929,39 @@ processInstruction(MCInst &Inst,
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return true;
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}
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case ARM::VLD4LNdAsm_8:
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case ARM::VLD4LNdAsm_16:
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case ARM::VLD4LNdAsm_32:
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case ARM::VLD4LNqAsm_16:
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case ARM::VLD4LNqAsm_32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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// VLD3 multiple 3-element structure instructions.
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case ARM::VLD3dAsm_8:
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case ARM::VLD3dAsm_16:
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@ -336,17 +336,39 @@
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@ CHECK: vld3.32 {d5[0], d7[0], d9[0]}, [r4]! @ encoding: [0x4d,0x5a,0xa4,0xf4]
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@ vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
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@ vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
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@ vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
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@ vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64]
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@ vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
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vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]
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vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]
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vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]
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vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]
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vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]
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@ FIXME: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xe0,0xf4]
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@ FIXME: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf4]
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@ FIXME: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf4]
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@ FIXME: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf4]
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@ FIXME: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf4]
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vld4.s8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]!
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vld4.s16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]!
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vld4.s32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]!
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vld4.u16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!
|
||||
vld4.u32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!
|
||||
|
||||
vld4.p8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8
|
||||
vld4.p16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7
|
||||
vld4.f32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5
|
||||
vld4.i16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3
|
||||
vld4.i32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4
|
||||
|
||||
@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1] @ encoding: [0x2f,0x03,0xe1,0xf4]
|
||||
@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2] @ encoding: [0x4f,0x07,0xe2,0xf4]
|
||||
@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] @ encoding: [0x8f,0x0b,0xe3,0xf4]
|
||||
@ CHECK: vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] @ encoding: [0x6f,0x17,0xe7,0xf4]
|
||||
@ CHECK: vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] @ encoding: [0xcf,0x0b,0xe8,0xf4]
|
||||
@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! @ encoding: [0x3d,0x03,0xe1,0xf4]
|
||||
@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]! @ encoding: [0x5d,0x07,0xe2,0xf4]
|
||||
@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]! @ encoding: [0xad,0x0b,0xe3,0xf4]
|
||||
@ CHECK: vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! @ encoding: [0x6d,0x17,0xe7,0xf4]
|
||||
@ CHECK: vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! @ encoding: [0xcd,0x0b,0xe8,0xf4]
|
||||
@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8 @ encoding: [0x38,0x03,0xe1,0xf4]
|
||||
@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 @ encoding: [0x47,0x07,0xe2,0xf4]
|
||||
@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5 @ encoding: [0x95,0x0b,0xe3,0xf4]
|
||||
@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 @ encoding: [0x63,0x07,0xe6,0xf4]
|
||||
@ CHECK: vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 @ encoding: [0xc4,0x1b,0xe9,0xf4]
|
||||
|
||||
|
||||
@ Handle 'Q' registers in register lists as if the sub-reg D regs were
|
||||
|
||||
Loading…
Reference in New Issue
Block a user