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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-02 22:30:36 +00:00
Move the legalization of vector loads and stores into LegalizeVectorOps. In some
cases we need the second type-legalization pass in order to support all cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142060 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
parent
365c9f1ff5
commit
e9b58d0aac
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@ -1369,89 +1369,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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break;
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}
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// If this is a promoted vector load, and the vector element types are
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// legal, then scalarize it.
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if (ExtType == ISD::EXTLOAD && SrcVT.isVector() &&
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TLI.isTypeLegal(Node->getValueType(0).getScalarType())) {
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SmallVector<SDValue, 8> LoadVals;
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SmallVector<SDValue, 8> LoadChains;
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unsigned NumElem = SrcVT.getVectorNumElements();
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unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
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for (unsigned Idx=0; Idx<NumElem; Idx++) {
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(Stride));
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SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
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Node->getValueType(0).getScalarType(),
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Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
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SrcVT.getScalarType(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->getAlignment());
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LoadVals.push_back(ScalarLoad.getValue(0));
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LoadChains.push_back(ScalarLoad.getValue(1));
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}
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Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&LoadChains[0], LoadChains.size());
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SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
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Node->getValueType(0), &LoadVals[0], LoadVals.size());
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Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
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Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
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break;
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}
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// If this is a promoted vector load, and the vector element types are
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// illegal, create the promoted vector from bitcasted segments.
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if (ExtType == ISD::EXTLOAD && SrcVT.isVector()) {
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EVT MemElemTy = Node->getValueType(0).getScalarType();
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EVT SrcSclrTy = SrcVT.getScalarType();
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unsigned SizeRatio =
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(MemElemTy.getSizeInBits() / SrcSclrTy.getSizeInBits());
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SmallVector<SDValue, 8> LoadVals;
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SmallVector<SDValue, 8> LoadChains;
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unsigned NumElem = SrcVT.getVectorNumElements();
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unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
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for (unsigned Idx=0; Idx<NumElem; Idx++) {
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(Stride));
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SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
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SrcVT.getScalarType(),
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Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
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SrcVT.getScalarType(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->getAlignment());
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if (TLI.isBigEndian()) {
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// MSB (which is garbage, comes first)
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LoadVals.push_back(ScalarLoad.getValue(0));
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for (unsigned i = 0; i<SizeRatio-1; ++i)
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LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
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} else {
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// LSB (which is data, comes first)
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for (unsigned i = 0; i<SizeRatio-1; ++i)
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LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
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LoadVals.push_back(ScalarLoad.getValue(0));
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}
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LoadChains.push_back(ScalarLoad.getValue(1));
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}
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Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&LoadChains[0], LoadChains.size());
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EVT TempWideVector = EVT::getVectorVT(*DAG.getContext(),
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SrcVT.getScalarType(), NumElem*SizeRatio);
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SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
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TempWideVector, &LoadVals[0], LoadVals.size());
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// Cast to the correct type
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ValRes = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), ValRes);
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Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
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Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
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break;
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}
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assert(!SrcVT.isVector() &&
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"Vector Loads are handled in LegalizeVectorOps");
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// FIXME: This does not work for vectors on most targets. Sign- and
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// zero-extend operations are currently folded into extending loads,
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@ -1628,106 +1547,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Result = TLI.LowerOperation(Result, DAG);
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break;
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case TargetLowering::Expand:
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EVT WideScalarVT = Tmp3.getValueType().getScalarType();
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EVT NarrowScalarVT = StVT.getScalarType();
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if (StVT.isVector()) {
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unsigned NumElem = StVT.getVectorNumElements();
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// The type of the data we want to save
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EVT RegVT = Tmp3.getValueType();
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EVT RegSclVT = RegVT.getScalarType();
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// The type of data as saved in memory.
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EVT MemSclVT = StVT.getScalarType();
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bool RegScalarLegal = TLI.isTypeLegal(RegSclVT);
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bool MemScalarLegal = TLI.isTypeLegal(MemSclVT);
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// We need to expand this store. If the register element type
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// is legal then we can scalarize the vector and use
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// truncating stores.
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if (RegScalarLegal) {
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// Cast floats into integers
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unsigned ScalarSize = MemSclVT.getSizeInBits();
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EVT EltVT = EVT::getIntegerVT(*DAG.getContext(), ScalarSize);
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// Round odd types to the next pow of two.
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if (!isPowerOf2_32(ScalarSize))
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ScalarSize = NextPowerOf2(ScalarSize);
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// Store Stride in bytes
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unsigned Stride = ScalarSize/8;
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// Extract each of the elements from the original vector
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// and save them into memory individually.
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SmallVector<SDValue, 8> Stores;
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for (unsigned Idx = 0; Idx < NumElem; Idx++) {
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SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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RegSclVT, Tmp3, DAG.getIntPtrConstant(Idx));
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(Stride));
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// This scalar TruncStore may be illegal, but we lehalize it
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// later.
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SDValue Store = DAG.getTruncStore(Tmp1, dl, Ex, Tmp2,
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ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
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isVolatile, isNonTemporal, Alignment);
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Stores.push_back(Store);
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}
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Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&Stores[0], Stores.size());
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break;
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}
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// The scalar register type is illegal.
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// For example saving <2 x i64> -> <2 x i32> on a x86.
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// In here we bitcast the value into a vector of smaller parts and
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// save it using smaller scalars.
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if (!RegScalarLegal && MemScalarLegal) {
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// Store Stride in bytes
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unsigned Stride = MemSclVT.getSizeInBits()/8;
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unsigned SizeRatio =
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(RegSclVT.getSizeInBits() / MemSclVT.getSizeInBits());
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EVT CastValueVT = EVT::getVectorVT(*DAG.getContext(),
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MemSclVT,
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SizeRatio * NumElem);
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// Cast the wide elem vector to wider vec with smaller elem type.
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// Example <2 x i64> -> <4 x i32>
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Tmp3 = DAG.getNode(ISD::BITCAST, dl, CastValueVT, Tmp3);
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SmallVector<SDValue, 8> Stores;
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for (unsigned Idx=0; Idx < NumElem * SizeRatio; Idx++) {
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// Extract the Ith element.
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SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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NarrowScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
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// Bump pointer.
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(Stride));
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// Store if, this element is:
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// - First element on big endian, or
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// - Last element on little endian
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if (( TLI.isBigEndian() && (Idx % SizeRatio == 0)) ||
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((!TLI.isBigEndian() && (Idx % SizeRatio == SizeRatio-1)))) {
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SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
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ST->getPointerInfo().getWithOffset(Idx*Stride),
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isVolatile, isNonTemporal, Alignment);
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Stores.push_back(Store);
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}
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}
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Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&Stores[0], Stores.size());
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break;
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}
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assert(false && "Unable to legalize the vector trunc store!");
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}// is vector
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assert(!StVT.isVector() &&
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"Vector Stores are handled in LegalizeVectorOps");
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// TRUNCSTORE:i16 i32 -> STORE i16
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assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
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@ -64,6 +64,8 @@ class VectorLegalizer {
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// Implement vselect in terms of XOR, AND, OR when blend is not supported
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// by the target.
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SDValue ExpandVSELECT(SDValue Op);
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SDValue ExpandLoad(SDValue Op);
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SDValue ExpandStore(SDValue Op);
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SDValue ExpandFNEG(SDValue Op);
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// Implements vector promotion; this is essentially just bitcasting the
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// operands to a different type and bitcasting the result back to the
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@ -124,6 +126,33 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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SDValue Result =
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SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0);
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if (Op.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
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if (TLI.isLoadExtLegal(LD->getExtensionType(), LD->getMemoryVT()))
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return TranslateLegalizeResults(Op, Result);
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Changed = true;
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return LegalizeOp(ExpandLoad(Op));
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}
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} else if (Op.getOpcode() == ISD::STORE) {
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StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
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EVT StVT = ST->getMemoryVT();
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EVT ValVT = ST->getValue().getValueType();
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if (StVT.isVector() && ST->isTruncatingStore())
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switch (TLI.getTruncStoreAction(ValVT, StVT)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal:
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return TranslateLegalizeResults(Op, Result);
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case TargetLowering::Custom:
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Changed = true;
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return LegalizeOp(TLI.LowerOperation(Result, DAG));
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case TargetLowering::Expand:
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Changed = true;
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return LegalizeOp(ExpandStore(Op));
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}
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}
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bool HasVectorValue = false;
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for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
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J != E;
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@ -262,6 +291,96 @@ SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
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return DAG.getNode(ISD::BITCAST, dl, VT, Op);
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}
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SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
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DebugLoc dl = Op.getDebugLoc();
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LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
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SDValue Chain = LD->getChain();
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SDValue BasePTR = LD->getBasePtr();
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EVT SrcVT = LD->getMemoryVT();
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SmallVector<SDValue, 8> LoadVals;
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SmallVector<SDValue, 8> LoadChains;
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unsigned NumElem = SrcVT.getVectorNumElements();
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unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
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for (unsigned Idx=0; Idx<NumElem; Idx++) {
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BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
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DAG.getIntPtrConstant(Stride));
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SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
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Op.getNode()->getValueType(0).getScalarType(),
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Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
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SrcVT.getScalarType(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->getAlignment());
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LoadVals.push_back(ScalarLoad.getValue(0));
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LoadChains.push_back(ScalarLoad.getValue(1));
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}
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SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&LoadChains[0], LoadChains.size());
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SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
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Op.getNode()->getValueType(0), &LoadVals[0], LoadVals.size());
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AddLegalizedOperand(Op.getValue(0), Value);
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AddLegalizedOperand(Op.getValue(1), NewChain);
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return (Op.getResNo() ? NewChain : Value);
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}
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SDValue VectorLegalizer::ExpandStore(SDValue Op) {
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DebugLoc dl = Op.getDebugLoc();
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StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
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SDValue Chain = ST->getChain();
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SDValue BasePTR = ST->getBasePtr();
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SDValue Value = ST->getValue();
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EVT StVT = ST->getMemoryVT();
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unsigned Alignment = ST->getAlignment();
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bool isVolatile = ST->isVolatile();
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bool isNonTemporal = ST->isNonTemporal();
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unsigned NumElem = StVT.getVectorNumElements();
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// The type of the data we want to save
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EVT RegVT = Value.getValueType();
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EVT RegSclVT = RegVT.getScalarType();
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// The type of data as saved in memory.
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EVT MemSclVT = StVT.getScalarType();
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// Cast floats into integers
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unsigned ScalarSize = MemSclVT.getSizeInBits();
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EVT EltVT = EVT::getIntegerVT(*DAG.getContext(), ScalarSize);
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// Round odd types to the next pow of two.
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if (!isPowerOf2_32(ScalarSize))
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ScalarSize = NextPowerOf2(ScalarSize);
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// Store Stride in bytes
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unsigned Stride = ScalarSize/8;
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// Extract each of the elements from the original vector
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// and save them into memory individually.
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SmallVector<SDValue, 8> Stores;
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for (unsigned Idx = 0; Idx < NumElem; Idx++) {
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SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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RegSclVT, Value, DAG.getIntPtrConstant(Idx));
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BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
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DAG.getIntPtrConstant(Stride));
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// This scalar TruncStore may be illegal, but we legalize it later.
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SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
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ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
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isVolatile, isNonTemporal, Alignment);
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Stores.push_back(Store);
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}
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SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&Stores[0], Stores.size());
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AddLegalizedOperand(Op, TF);
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return TF;
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}
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SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
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// Implement VSELECT in terms of XOR, AND, OR
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// on platforms which do not support blend natively.
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