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https://github.com/c64scene-ar/llvm-6502.git
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* Add utility functions: convert SetCC => PPC opcode and invert PPC opcode
* If SetCondInst is folded into BranchInst (and it is the only user), do not emit code for SetCondInst * Fix assembly opcodes in comments in visitSetCondInst() * Fix codegen of conditional branches git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14643 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -722,7 +722,7 @@ static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
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// order of the opcodes.
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//
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static unsigned getSetCCNumber(unsigned Opcode) {
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switch(Opcode) {
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switch (Opcode) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: return 0;
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case Instruction::SetNE: return 1;
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@ -733,6 +733,30 @@ static unsigned getSetCCNumber(unsigned Opcode) {
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}
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}
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static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
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switch (Opcode) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: return PPC32::BEQ;
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case Instruction::SetNE: return PPC32::BNE;
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case Instruction::SetLT: return PPC32::BLT;
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case Instruction::SetGE: return PPC32::BGE;
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case Instruction::SetGT: return PPC32::BGT;
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case Instruction::SetLE: return PPC32::BLE;
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}
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}
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static unsigned invertPPCBranchOpcode(unsigned Opcode) {
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switch (Opcode) {
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default: assert(0 && "Unknown PPC32 branch opcode!");
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case PPC32::BEQ: return PPC32::BNE;
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case PPC32::BNE: return PPC32::BEQ;
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case PPC32::BLT: return PPC32::BGE;
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case PPC32::BGE: return PPC32::BLT;
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case PPC32::BGT: return PPC32::BLE;
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case PPC32::BLE: return PPC32::BGT;
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}
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}
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/// emitUCOM - emits an unordered FP compare.
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void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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unsigned LHS, unsigned RHS) {
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@ -751,7 +775,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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// Special case handling of: cmp R, i
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if (isa<ConstantPointerNull>(Op1)) {
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BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
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BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
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} else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
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if (Class == cByte || Class == cShort || Class == cInt) {
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unsigned Op1v = CI->getRawValue();
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@ -839,6 +863,17 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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/// visitSetCondInst -
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///
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void ISel::visitSetCondInst(SetCondInst &I) {
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// If the only user of this SetCC is a branch or a select, we don't have to
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// code-gen this instruction, it will be done more compactly for us later.
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// FIXME: perhaps there could be several branches/selects using this SetCC and
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// this SetCC could still be a valid candidate for folding? Then the problem
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// becomes with live range, whether or not the uses span function calls, other
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// branches with can overwrite the condition register, etc.
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User *user = I.hasOneUse() ? I.use_back() : 0;
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if (canFoldSetCCIntoBranchOrSelect(&I) &&
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(isa<BranchInst>(user) || isa<SelectInst>(user)))
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return;
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unsigned Op0Reg = getReg(I.getOperand(0));
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unsigned Op1Reg = getReg(I.getOperand(1));
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unsigned DestReg = getReg(I);
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@ -848,21 +883,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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// Compare the two values.
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BuildMI(BB, PPC32::CMPW, 2, PPC32::CR0).addReg(Op0Reg).addReg(Op1Reg);
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unsigned BranchIdx;
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switch (I.getOpcode()) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: BranchIdx = 0; break;
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case Instruction::SetNE: BranchIdx = 1; break;
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case Instruction::SetLT: BranchIdx = 2; break;
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case Instruction::SetGT: BranchIdx = 3; break;
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case Instruction::SetLE: BranchIdx = 4; break;
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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static unsigned OpcodeTab[] = {
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PPC32::BEQ, PPC32::BNE, PPC32::BLT, PPC32::BGT, PPC32::BLE, PPC32::BGE
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};
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unsigned Opcode = OpcodeTab[BranchIdx];
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unsigned Opcode = getPPCOpcodeForSetCCNumber(I.getOpcode());
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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// thisMBB:
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@ -886,7 +907,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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// copy0MBB:
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// %FalseValue = li 0
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// ba sinkMBB
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// b sinkMBB
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BB = copy0MBB;
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unsigned FalseValue = makeAnotherReg(I.getType());
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BuildMI(BB, PPC32::LI, 1, FalseValue).addZImm(0);
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@ -903,7 +924,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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// copy1MBB:
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// %TrueValue = li 1
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// ba sinkMBB
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// b sinkMBB
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BB = copy1MBB;
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unsigned TrueValue = makeAnotherReg (I.getType ());
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BuildMI(BB, PPC32::LI, 1, TrueValue).addZImm(1);
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@ -1091,9 +1112,9 @@ void ISel::visitBranchInst(BranchInst &BI) {
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BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
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BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
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if (!BI.isConditional()) { // Unconditional branch?
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if (BI.getSuccessor(0) != NextBB)
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
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return;
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}
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@ -1104,14 +1125,14 @@ void ISel::visitBranchInst(BranchInst &BI) {
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// Nope, cannot fold setcc into this branch. Emit a branch on a condition
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// computed some other way...
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unsigned condReg = getReg(BI.getCondition());
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BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(condReg)
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BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR1).addImm(0).addReg(condReg)
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.addImm(0);
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if (BI.getSuccessor(1) == NextBB) {
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, PPC32::BC, 3).addImm(4).addImm(2)
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BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
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.addMBB(MBBMap[BI.getSuccessor(0)]);
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} else {
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BuildMI(BB, PPC32::BC, 3).addImm(12).addImm(2)
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BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
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.addMBB(MBBMap[BI.getSuccessor(1)]);
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if (BI.getSuccessor(0) != NextBB)
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@ -1121,26 +1142,20 @@ void ISel::visitBranchInst(BranchInst &BI) {
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}
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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unsigned Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
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MachineBasicBlock::iterator MII = BB->end();
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OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
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const Type *CompTy = SCI->getOperand(0)->getType();
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bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
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static const unsigned BITab[6] = { 2, 2, 0, 0, 1, 1 };
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unsigned BO_true = (OpNum % 2 == 0) ? 12 : 4;
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unsigned BO_false = (OpNum % 2 == 0) ? 4 : 12;
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unsigned BIval = BITab[0];
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if (BI.getSuccessor(0) != NextBB) {
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BuildMI(BB, PPC32::BC, 3).addImm(BO_true).addImm(BIval)
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BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
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.addMBB(MBBMap[BI.getSuccessor(0)]);
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if (BI.getSuccessor(1) != NextBB)
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BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
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} else {
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// Change to the inverse condition...
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if (BI.getSuccessor(1) != NextBB) {
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BuildMI(BB, PPC32::BC, 3).addImm(BO_false).addImm(BIval)
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Opcode = invertPPCBranchOpcode(Opcode);
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BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
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.addMBB(MBBMap[BI.getSuccessor(1)]);
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}
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}
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@ -722,7 +722,7 @@ static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
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// order of the opcodes.
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//
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static unsigned getSetCCNumber(unsigned Opcode) {
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switch(Opcode) {
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switch (Opcode) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: return 0;
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case Instruction::SetNE: return 1;
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@ -733,6 +733,30 @@ static unsigned getSetCCNumber(unsigned Opcode) {
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}
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}
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static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
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switch (Opcode) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: return PPC32::BEQ;
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case Instruction::SetNE: return PPC32::BNE;
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case Instruction::SetLT: return PPC32::BLT;
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case Instruction::SetGE: return PPC32::BGE;
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case Instruction::SetGT: return PPC32::BGT;
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case Instruction::SetLE: return PPC32::BLE;
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}
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}
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static unsigned invertPPCBranchOpcode(unsigned Opcode) {
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switch (Opcode) {
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default: assert(0 && "Unknown PPC32 branch opcode!");
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case PPC32::BEQ: return PPC32::BNE;
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case PPC32::BNE: return PPC32::BEQ;
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case PPC32::BLT: return PPC32::BGE;
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case PPC32::BGE: return PPC32::BLT;
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case PPC32::BGT: return PPC32::BLE;
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case PPC32::BLE: return PPC32::BGT;
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}
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}
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/// emitUCOM - emits an unordered FP compare.
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void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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unsigned LHS, unsigned RHS) {
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@ -751,7 +775,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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// Special case handling of: cmp R, i
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if (isa<ConstantPointerNull>(Op1)) {
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BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
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BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
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} else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
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if (Class == cByte || Class == cShort || Class == cInt) {
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unsigned Op1v = CI->getRawValue();
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@ -839,6 +863,17 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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/// visitSetCondInst -
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///
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void ISel::visitSetCondInst(SetCondInst &I) {
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// If the only user of this SetCC is a branch or a select, we don't have to
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// code-gen this instruction, it will be done more compactly for us later.
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// FIXME: perhaps there could be several branches/selects using this SetCC and
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// this SetCC could still be a valid candidate for folding? Then the problem
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// becomes with live range, whether or not the uses span function calls, other
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// branches with can overwrite the condition register, etc.
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User *user = I.hasOneUse() ? I.use_back() : 0;
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if (canFoldSetCCIntoBranchOrSelect(&I) &&
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(isa<BranchInst>(user) || isa<SelectInst>(user)))
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return;
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unsigned Op0Reg = getReg(I.getOperand(0));
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unsigned Op1Reg = getReg(I.getOperand(1));
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unsigned DestReg = getReg(I);
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@ -848,21 +883,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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// Compare the two values.
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BuildMI(BB, PPC32::CMPW, 2, PPC32::CR0).addReg(Op0Reg).addReg(Op1Reg);
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unsigned BranchIdx;
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switch (I.getOpcode()) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: BranchIdx = 0; break;
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case Instruction::SetNE: BranchIdx = 1; break;
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case Instruction::SetLT: BranchIdx = 2; break;
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case Instruction::SetGT: BranchIdx = 3; break;
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case Instruction::SetLE: BranchIdx = 4; break;
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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static unsigned OpcodeTab[] = {
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PPC32::BEQ, PPC32::BNE, PPC32::BLT, PPC32::BGT, PPC32::BLE, PPC32::BGE
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};
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unsigned Opcode = OpcodeTab[BranchIdx];
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unsigned Opcode = getPPCOpcodeForSetCCNumber(I.getOpcode());
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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// thisMBB:
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@ -886,7 +907,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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// copy0MBB:
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// %FalseValue = li 0
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// ba sinkMBB
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// b sinkMBB
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BB = copy0MBB;
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unsigned FalseValue = makeAnotherReg(I.getType());
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BuildMI(BB, PPC32::LI, 1, FalseValue).addZImm(0);
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@ -903,7 +924,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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// copy1MBB:
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// %TrueValue = li 1
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// ba sinkMBB
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// b sinkMBB
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BB = copy1MBB;
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unsigned TrueValue = makeAnotherReg (I.getType ());
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BuildMI(BB, PPC32::LI, 1, TrueValue).addZImm(1);
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@ -1091,9 +1112,9 @@ void ISel::visitBranchInst(BranchInst &BI) {
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BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
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BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
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if (!BI.isConditional()) { // Unconditional branch?
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if (BI.getSuccessor(0) != NextBB)
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
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return;
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}
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@ -1104,14 +1125,14 @@ void ISel::visitBranchInst(BranchInst &BI) {
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// Nope, cannot fold setcc into this branch. Emit a branch on a condition
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// computed some other way...
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unsigned condReg = getReg(BI.getCondition());
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BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(condReg)
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BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR1).addImm(0).addReg(condReg)
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.addImm(0);
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if (BI.getSuccessor(1) == NextBB) {
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, PPC32::BC, 3).addImm(4).addImm(2)
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BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
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.addMBB(MBBMap[BI.getSuccessor(0)]);
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} else {
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BuildMI(BB, PPC32::BC, 3).addImm(12).addImm(2)
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BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
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.addMBB(MBBMap[BI.getSuccessor(1)]);
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if (BI.getSuccessor(0) != NextBB)
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@ -1121,26 +1142,20 @@ void ISel::visitBranchInst(BranchInst &BI) {
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}
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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unsigned Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
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MachineBasicBlock::iterator MII = BB->end();
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OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
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const Type *CompTy = SCI->getOperand(0)->getType();
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bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
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static const unsigned BITab[6] = { 2, 2, 0, 0, 1, 1 };
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unsigned BO_true = (OpNum % 2 == 0) ? 12 : 4;
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unsigned BO_false = (OpNum % 2 == 0) ? 4 : 12;
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unsigned BIval = BITab[0];
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if (BI.getSuccessor(0) != NextBB) {
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BuildMI(BB, PPC32::BC, 3).addImm(BO_true).addImm(BIval)
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BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
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.addMBB(MBBMap[BI.getSuccessor(0)]);
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if (BI.getSuccessor(1) != NextBB)
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BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
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} else {
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// Change to the inverse condition...
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if (BI.getSuccessor(1) != NextBB) {
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BuildMI(BB, PPC32::BC, 3).addImm(BO_false).addImm(BIval)
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Opcode = invertPPCBranchOpcode(Opcode);
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BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
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.addMBB(MBBMap[BI.getSuccessor(1)]);
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}
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}
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