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https://github.com/c64scene-ar/llvm-6502.git
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Add support for truncstore and *extload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19566 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -53,7 +53,7 @@ namespace {
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setOperationUnsupported(ISD::MEMMOVE, MVT::Other);
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setOperationUnsupported(ISD::MUL, MVT::i8);
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//setOperationUnsupported(ISD::SEXTLOAD, MVT::i1);
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setOperationUnsupported(ISD::SELECT, MVT::i1);
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setOperationUnsupported(ISD::SELECT, MVT::i8);
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@ -1957,7 +1957,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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EmitSetCC(BB, Result, cast<SetCCSDNode>(N)->getCondition(),
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MVT::isFloatingPoint(N.getOperand(1).getValueType()));
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return Result;
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case ISD::LOAD: {
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case ISD::LOAD:
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// Make sure we generate both values.
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1; // Generate the token
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@ -1993,7 +1993,99 @@ unsigned ISel::SelectExpr(SDOperand N) {
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addFullAddress(BuildMI(BB, Opc, 4, Result), AM);
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}
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return Result;
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case ISD::EXTLOAD: // Arbitrarily codegen extloads as MOVZX*
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case ISD::ZEXTLOAD: {
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// Make sure we generate both values.
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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X86AddressMode AM;
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if (getRegPressure(Node->getOperand(0)) >
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getRegPressure(Node->getOperand(1))) {
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Select(Node->getOperand(0)); // chain
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SelectAddress(Node->getOperand(1), AM);
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} else {
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SelectAddress(Node->getOperand(1), AM);
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Select(Node->getOperand(0)); // chain
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}
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switch (Node->getValueType(0)) {
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default: assert(0 && "Unknown type to sign extend to.");
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case MVT::f64:
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assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
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"Bad EXTLOAD!");
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addFullAddress(BuildMI(BB, X86::FLD32m, 5, Result), AM);
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break;
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case MVT::i32:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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assert(0 && "Bad zero extend!");
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case MVT::i1:
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case MVT::i8:
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addFullAddress(BuildMI(BB, X86::MOVZX32rm8, 5, Result), AM);
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break;
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case MVT::i16:
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addFullAddress(BuildMI(BB, X86::MOVZX32rm16, 5, Result), AM);
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break;
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}
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break;
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case MVT::i16:
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assert(cast<MVTSDNode>(Node)->getExtraValueType() <= MVT::i8 &&
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"Bad zero extend!");
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addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM);
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break;
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case MVT::i8:
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assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i1 &&
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"Bad zero extend!");
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addFullAddress(BuildMI(BB, X86::MOV8rm, 5, Result), AM);
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break;
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}
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return Result;
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}
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case ISD::SEXTLOAD: {
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// Make sure we generate both values.
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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X86AddressMode AM;
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if (getRegPressure(Node->getOperand(0)) >
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getRegPressure(Node->getOperand(1))) {
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Select(Node->getOperand(0)); // chain
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SelectAddress(Node->getOperand(1), AM);
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} else {
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SelectAddress(Node->getOperand(1), AM);
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Select(Node->getOperand(0)); // chain
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}
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switch (Node->getValueType(0)) {
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case MVT::i8: assert(0 && "Cannot sign extend from bool!");
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default: assert(0 && "Unknown type to sign extend to.");
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case MVT::i32:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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case MVT::i1: assert(0 && "Cannot sign extend from bool!");
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case MVT::i8:
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addFullAddress(BuildMI(BB, X86::MOVSX32rm8, 5, Result), AM);
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break;
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case MVT::i16:
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addFullAddress(BuildMI(BB, X86::MOVSX32rm16, 5, Result), AM);
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break;
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}
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break;
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case MVT::i16:
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assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i8 &&
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"Cannot sign extend from bool!");
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addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM);
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break;
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}
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return Result;
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}
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case ISD::DYNAMIC_STACKALLOC:
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// Generate both result values.
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if (Result != 1)
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@ -2216,11 +2308,59 @@ void ISel::Select(SDOperand N) {
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return;
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}
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case ISD::EXTLOAD:
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case ISD::SEXTLOAD:
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case ISD::ZEXTLOAD:
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case ISD::LOAD:
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case ISD::CALL:
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case ISD::DYNAMIC_STACKALLOC:
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SelectExpr(N);
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return;
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case ISD::TRUNCSTORE: { // truncstore chain, val, ptr :storety
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// On X86, we can represent all types except for Bool and Float natively.
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X86AddressMode AM;
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MVT::ValueType StoredTy = cast<MVTSDNode>(Node)->getExtraValueType();
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assert((StoredTy == MVT::i1 || StoredTy == MVT::f32) &&
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"Unsupported TRUNCSTORE for this target!");
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// Store of constant bool?
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
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Select(N.getOperand(0));
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SelectAddress(N.getOperand(2), AM);
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} else {
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SelectAddress(N.getOperand(2), AM);
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Select(N.getOperand(0));
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}
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addFullAddress(BuildMI(BB, X86::MOV8mi, 5), AM).addImm(CN->getValue());
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return;
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}
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switch (StoredTy) {
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default: assert(0 && "Cannot truncstore this type!");
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case MVT::i1: Opc = X86::MOV8mr; break;
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case MVT::f32: Opc = X86::FST32m; break;
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}
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std::vector<std::pair<unsigned, unsigned> > RP;
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RP.push_back(std::make_pair(getRegPressure(N.getOperand(0)), 0));
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RP.push_back(std::make_pair(getRegPressure(N.getOperand(1)), 1));
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RP.push_back(std::make_pair(getRegPressure(N.getOperand(2)), 2));
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std::sort(RP.begin(), RP.end());
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for (unsigned i = 0; i != 3; ++i)
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switch (RP[2-i].second) {
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default: assert(0 && "Unknown operand number!");
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case 0: Select(N.getOperand(0)); break;
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case 1: Tmp1 = SelectExpr(N.getOperand(1)); break;
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case 2: SelectAddress(N.getOperand(2), AM); break;
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}
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addFullAddress(BuildMI(BB, Opc, 4+1), AM).addReg(Tmp1);
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return;
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}
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case ISD::STORE: {
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X86AddressMode AM;
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