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Minor stylistic cleanups in the Blackfin target.

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Thanks Chris.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77987 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2009-08-03 19:32:30 +00:00
parent cdc0654b3e
commit ea1c9b7bac
3 changed files with 46 additions and 42 deletions
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4
lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp
View File

@@ -159,8 +159,8 @@ void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
const TargetRegisterInfo &RI = *TM.getRegisterInfo(); const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) { switch (MO.getType()) {
case MachineOperand::MO_Register: case MachineOperand::MO_Register:
assert (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should be already mapped!"); "Virtual registers should be already mapped!");
O << RI.get(MO.getReg()).AsmName; O << RI.get(MO.getReg()).AsmName;
break; break;

12
lib/Target/Blackfin/BlackfinISelLowering.cpp
View File

@@ -188,8 +188,8 @@ SDValue BlackfinTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
MVT RegVT = VA.getLocVT(); MVT RegVT = VA.getLocVT();
TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ? TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
BF::PRegisterClass : BF::DRegisterClass; BF::PRegisterClass : BF::DRegisterClass;
assert(RC->contains(VA.getLocReg())); assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
assert(RC->hasType(RegVT)); assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
unsigned Reg = MF.getRegInfo().createVirtualRegister(RC); unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg); MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
@@ -210,7 +210,7 @@ SDValue BlackfinTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
ArgValues.push_back(ArgValue); ArgValues.push_back(ArgValue);
} else { } else {
assert(VA.isMemLoc()); assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
unsigned ObjSize = VA.getLocVT().getStoreSizeInBits()/8; unsigned ObjSize = VA.getLocVT().getStoreSizeInBits()/8;
int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset()); int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
@@ -331,10 +331,10 @@ SDValue BlackfinTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
if (VA.isRegLoc()) { if (VA.isRegLoc()) {
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
} else { } else {
assert(VA.isMemLoc()); assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
int Offset = VA.getLocMemOffset(); int Offset = VA.getLocMemOffset();
assert(Offset%4 == 0); assert(Offset%4 == 0 && "Unaligned LocMemOffset");
assert(VA.getLocVT()==MVT::i32); assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32); SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
SDValue OffsetN = DAG.getIntPtrConstant(Offset); SDValue OffsetN = DAG.getIntPtrConstant(Offset);
OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN); OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);

72
lib/Target/Blackfin/BlackfinRegisterInfo.cpp
View File

@@ -126,13 +126,15 @@ void BlackfinRegisterInfo::adjustRegister(MachineBasicBlock &MBB,
// We must load delta into ScratchReg and add that. // We must load delta into ScratchReg and add that.
loadConstant(MBB, I, DL, ScratchReg, delta); loadConstant(MBB, I, DL, ScratchReg, delta);
if (BF::PRegClass.contains(Reg)) { if (BF::PRegClass.contains(Reg)) {
assert (BF::PRegClass.contains(ScratchReg)); assert(BF::PRegClass.contains(ScratchReg) &&
"ScratchReg must be a P register");
BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg) BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
.addReg(Reg, RegState::Kill) .addReg(Reg, RegState::Kill)
.addReg(ScratchReg, RegState::Kill); .addReg(ScratchReg, RegState::Kill);
} else { } else {
assert (BF::DRegClass.contains(Reg)); assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
assert (BF::DRegClass.contains(ScratchReg)); assert(BF::DRegClass.contains(ScratchReg) &&
"ScratchReg must be a D register");
BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg) BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
.addReg(Reg, RegState::Kill) .addReg(Reg, RegState::Kill)
.addReg(ScratchReg, RegState::Kill); .addReg(ScratchReg, RegState::Kill);
@@ -179,11 +181,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF,
if (!hasReservedCallFrame(MF)) { if (!hasReservedCallFrame(MF)) {
int64_t Amount = I->getOperand(0).getImm(); int64_t Amount = I->getOperand(0).getImm();
if (Amount != 0) { if (Amount != 0) {
assert(Amount%4 == 0); assert(Amount%4 == 0 && "Unaligned call frame size");
if (I->getOpcode() == BF::ADJCALLSTACKDOWN) { if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount); adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount);
} else { } else {
assert(I->getOpcode() == BF::ADJCALLSTACKUP); assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
"Unknown call frame pseudo instruction");
adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount); adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount);
} }
} }
@@ -207,22 +210,23 @@ static unsigned findScratchRegister(MachineBasicBlock::iterator II,
void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, int SPAdj,
RegScavenger *RS) const { RegScavenger *RS) const {
unsigned i;
MachineInstr &MI = *II; MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent(); MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
DebugLoc DL = MI.getDebugLoc(); DebugLoc DL = MI.getDebugLoc();
for (i=0; !MI.getOperand(i).isFI(); i++) { unsigned FIPos;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); for (FIPos=0; !MI.getOperand(FIPos).isFI(); ++FIPos) {
assert(FIPos < MI.getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
} }
int FrameIndex = MI.getOperand(i).getIndex(); int FrameIndex = MI.getOperand(FIPos).getIndex();
assert(i+1 < MI.getNumOperands() && MI.getOperand(i+1).isImm()); assert(FIPos+1 < MI.getNumOperands() && MI.getOperand(FIPos+1).isImm());
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex)
+ MI.getOperand(i+1).getImm(); + MI.getOperand(FIPos+1).getImm();
unsigned BaseReg = BF::FP; unsigned BaseReg = BF::FP;
if (hasFP(MF)) { if (hasFP(MF)) {
assert(SPAdj==0); assert(SPAdj==0 && "Unexpected SP adjust in function with frame pointer");
} else { } else {
BaseReg = BF::SP; BaseReg = BF::SP;
Offset += MF.getFrameInfo()->getStackSize() + SPAdj; Offset += MF.getFrameInfo()->getStackSize() + SPAdj;
@@ -234,10 +238,10 @@ void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
case BF::STORE32fi: case BF::STORE32fi:
isStore = true; isStore = true;
case BF::LOAD32fi: { case BF::LOAD32fi: {
assert(Offset%4 == 0 && "Badly aligned i32 stack access"); assert(Offset%4 == 0 && "Unaligned i32 stack access");
assert(i==1); assert(FIPos==1 && "Bad frame index operand");
MI.getOperand(i).ChangeToRegister(BaseReg, false); MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
MI.getOperand(i+1).setImm(Offset); MI.getOperand(FIPos+1).setImm(Offset);
if (isUimm<6>(Offset)) { if (isUimm<6>(Offset)) {
MI.setDesc(TII.get(isStore MI.setDesc(TII.get(isStore
? BF::STORE32p_uimm6m4 ? BF::STORE32p_uimm6m4
@@ -248,7 +252,7 @@ void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.setDesc(TII.get(isStore MI.setDesc(TII.get(isStore
? BF::STORE32fp_nimm7m4 ? BF::STORE32fp_nimm7m4
: BF::LOAD32fp_nimm7m4)); : BF::LOAD32fp_nimm7m4));
MI.getOperand(i+1).setImm(-Offset); MI.getOperand(FIPos+1).setImm(-Offset);
return; return;
} }
if (isImm<18>(Offset)) { if (isImm<18>(Offset)) {
@@ -263,12 +267,12 @@ void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
break; break;
} }
case BF::ADDpp: { case BF::ADDpp: {
assert(MI.getOperand(0).isReg()); assert(MI.getOperand(0).isReg() && "ADD instruction needs a register");
unsigned DestReg = MI.getOperand(0).getReg(); unsigned DestReg = MI.getOperand(0).getReg();
// We need to produce a stack offset in a P register. We emit: // We need to produce a stack offset in a P register. We emit:
// P0 = offset; // P0 = offset;
// P0 = BR + P0; // P0 = BR + P0;
assert(i==1); assert(FIPos==1 && "Bad frame index operand");
loadConstant(MBB, II, DL, DestReg, Offset); loadConstant(MBB, II, DL, DestReg, Offset);
MI.getOperand(1).ChangeToRegister(DestReg, false, false, true); MI.getOperand(1).ChangeToRegister(DestReg, false, false, true);
MI.getOperand(2).ChangeToRegister(BaseReg, false); MI.getOperand(2).ChangeToRegister(BaseReg, false);
@@ -277,11 +281,11 @@ void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
case BF::STORE16fi: case BF::STORE16fi:
isStore = true; isStore = true;
case BF::LOAD16fi: { case BF::LOAD16fi: {
assert(Offset%2 == 0 && "Badly aligned i16 stack access"); assert(Offset%2 == 0 && "Unaligned i16 stack access");
assert(i==1); assert(FIPos==1 && "Bad frame index operand");
// We need a P register to use as an address // We need a P register to use as an address
unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj); unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj);
assert(ScratchReg); assert(ScratchReg && "Could not scavenge register");
loadConstant(MBB, II, DL, ScratchReg, Offset); loadConstant(MBB, II, DL, ScratchReg, Offset);
BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg) BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
.addReg(ScratchReg, RegState::Kill) .addReg(ScratchReg, RegState::Kill)
@@ -293,10 +297,10 @@ void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
} }
case BF::STORE8fi: { case BF::STORE8fi: {
// This is an AnyCC spill, we need a scratch register. // This is an AnyCC spill, we need a scratch register.
assert(i==1); assert(FIPos==1 && "Bad frame index operand");
MachineOperand SpillReg = MI.getOperand(0); MachineOperand SpillReg = MI.getOperand(0);
unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj); unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
assert(ScratchReg); assert(ScratchReg && "Could not scavenge register");
if (SpillReg.getReg()==BF::NCC) { if (SpillReg.getReg()==BF::NCC) {
BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg) BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg)
.addOperand(SpillReg); .addOperand(SpillReg);
@@ -309,20 +313,20 @@ void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// STORE D // STORE D
MI.setDesc(TII.get(BF::STORE8p_imm16)); MI.setDesc(TII.get(BF::STORE8p_imm16));
MI.getOperand(0).ChangeToRegister(ScratchReg, false, false, true); MI.getOperand(0).ChangeToRegister(ScratchReg, false, false, true);
MI.getOperand(i).ChangeToRegister(BaseReg, false); MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
MI.getOperand(i+1).setImm(Offset); MI.getOperand(FIPos+1).setImm(Offset);
break; break;
} }
case BF::LOAD8fi: { case BF::LOAD8fi: {
// This is an restore, we need a scratch register. // This is an restore, we need a scratch register.
assert(i==1); assert(FIPos==1 && "Bad frame index operand");
MachineOperand SpillReg = MI.getOperand(0); MachineOperand SpillReg = MI.getOperand(0);
unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj); unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
assert(ScratchReg); assert(ScratchReg && "Could not scavenge register");
MI.setDesc(TII.get(BF::LOAD32p_imm16_8z)); MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
MI.getOperand(0).ChangeToRegister(ScratchReg, true); MI.getOperand(0).ChangeToRegister(ScratchReg, true);
MI.getOperand(i).ChangeToRegister(BaseReg, false); MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
MI.getOperand(i+1).setImm(Offset); MI.getOperand(FIPos+1).setImm(Offset);
++II; ++II;
if (SpillReg.getReg()==BF::CC) { if (SpillReg.getReg()==BF::CC) {
// CC = D // CC = D
@@ -376,8 +380,8 @@ void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
} }
if (!hasFP(MF)) { if (!hasFP(MF)) {
// So far we only support FP elimination on leaf functions assert(!MFI->hasCalls() &&
assert(!MFI->hasCalls()); "FP elimination on a non-leaf function is not supported");
adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize); adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
return; return;
} }
@@ -417,8 +421,8 @@ void BlackfinRegisterInfo::emitEpilogue(MachineFunction &MF,
assert(FrameSize%4 == 0 && "Misaligned frame size"); assert(FrameSize%4 == 0 && "Misaligned frame size");
if (!hasFP(MF)) { if (!hasFP(MF)) {
// So far we only support FP elimination on leaf functions assert(!MFI->hasCalls() &&
assert(!MFI->hasCalls()); "FP elimination on a non-leaf function is not supported");
adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize); adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
return; return;
} }