mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Split the machine code emitter completely out of the printer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
3e80f7d9ce
commit
ea1ddab58e
@ -6,24 +6,35 @@
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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namespace {
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struct Emitter : public FunctionPass {
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class Emitter : public FunctionPass {
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X86TargetMachine &TM;
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const X86InstrInfo ⅈ
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MachineCodeEmitter &MCE;
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public:
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Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
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: TM(tm), II(TM.getInstrInfo()), MCE(mce) {}
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bool runOnFunction(Function &F);
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private:
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void emitBasicBlock(MachineBasicBlock &MBB);
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void emitInstruction(MachineInstr &MI);
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void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
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void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
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void emitConstant(unsigned Val, unsigned Size);
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void emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField);
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};
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}
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@ -56,6 +67,141 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
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emitInstruction(**I);
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}
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namespace N86 { // Native X86 Register numbers...
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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// getX86RegNum - This function maps LLVM register identifiers to their X86
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// specific numbering, which is used in various places encoding instructions.
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//
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static unsigned getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
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case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
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case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
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case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
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default:
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assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
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"Unknown physical register!");
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assert(0 && "Register allocator hasn't allocated reg correctly yet!");
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return 0;
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}
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}
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
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MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
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}
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void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
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// SIB byte is in the same format as the ModRMByte...
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MCE.emitByte(ModRMByte(SS, Index, Base));
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}
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void Emitter::emitConstant(unsigned Val, unsigned Size) {
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// Output the constant in little endian byte order...
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for (unsigned i = 0; i != Size; ++i) {
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MCE.emitByte(Val & 255);
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Val >>= 8;
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}
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}
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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void Emitter::emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField) {
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const MachineOperand &BaseReg = MI.getOperand(Op);
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const MachineOperand &Scale = MI.getOperand(Op+1);
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const MachineOperand &IndexReg = MI.getOperand(Op+2);
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const MachineOperand &Disp = MI.getOperand(Op+3);
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// Is a SIB byte needed?
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if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
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if (BaseReg.getReg() == 0) { // Just a displacement?
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// Emit special case [disp32] encoding
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
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emitConstant(Disp.getImmedValue(), 4);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
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// Emit simple indirect register encoding... [EAX] f.e.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
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} else if (isDisp8(Disp.getImmedValue())) {
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// Emit the disp8 encoding... [REG+disp8]
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MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(Disp.getImmedValue(), 1);
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(Disp.getImmedValue(), 4);
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}
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}
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} else { // We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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if (BaseReg.getReg() == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (Disp.getImmedValue() == 0) {
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// Emit no displacement ModR/M byte
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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} else if (isDisp8(Disp.getImmedValue())) {
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// Emit the disp8 encoding...
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MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
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} else {
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// Emit the normal disp32 encoding...
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MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImmedValue()];
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if (BaseReg.getReg() == 0) {
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// Handle the SIB byte for the case where there is no base. The
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// displacement has already been output.
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assert(IndexReg.getReg() && "Index register must be specified!");
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emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
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emitSIBByte(SS, IndexRegNo, BaseRegNo);
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}
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// Do we need to output a displacement?
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if (Disp.getImmedValue() != 0 || ForceDisp32) {
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if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
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emitConstant(Disp.getImmedValue(), 1);
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else
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emitConstant(Disp.getImmedValue(), 4);
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}
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}
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}
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static bool isImmediate(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
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MO.getType() == MachineOperand::MO_UnextendedImmed;
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}
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void Emitter::emitInstruction(MachineInstr &MI) {
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unsigned Opcode = MI.getOpcode();
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const MachineInstrDescriptor &Desc = II.get(Opcode);
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@ -64,15 +210,57 @@ void Emitter::emitInstruction(MachineInstr &MI) {
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
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if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix
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unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode);
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::RawFrm:
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MCE.emitByte(II.getBaseOpcodeFor(Opcode));
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MCE.emitByte(BaseOpcode);
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if (MI.getNumOperands() == 1) {
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assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp);
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MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue());
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}
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break;
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case X86II::AddRegFrm:
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MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
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if (MI.getNumOperands() == 2) {
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unsigned Size = 4;
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emitConstant(MI.getOperand(1).getImmedValue(), Size);
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}
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break;
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case X86II::MRMDestReg:
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MCE.emitByte(BaseOpcode);
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emitRegModRMByte(MI.getOperand(0).getReg(),
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getX86RegNum(MI.getOperand(MI.getNumOperands()-1).getReg()));
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break;
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case X86II::MRMDestMem:
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MCE.emitByte(BaseOpcode);
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emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
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break;
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case X86II::MRMSrcReg:
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MCE.emitByte(BaseOpcode);
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emitRegModRMByte(MI.getOperand(MI.getNumOperands()-1).getReg(),
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getX86RegNum(MI.getOperand(0).getReg()));
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break;
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case X86II::MRMSrcMem:
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MCE.emitByte(BaseOpcode);
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emitMemModRMByte(MI, MI.getNumOperands()-4,
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getX86RegNum(MI.getOperand(0).getReg()));
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break;
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case X86II::MRMS0r: case X86II::MRMS1r:
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case X86II::MRMS2r: case X86II::MRMS3r:
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case X86II::MRMS4r: case X86II::MRMS5r:
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case X86II::MRMS6r: case X86II::MRMS7r:
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MCE.emitByte(BaseOpcode);
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emitRegModRMByte(MI.getOperand(0).getReg(),
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(Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r);
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if (isImmediate(MI.getOperand(MI.getNumOperands()-1))) {
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unsigned Size = 4;
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emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);
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}
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break;
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}
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}
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@ -108,7 +108,7 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp:
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O << "< " << MO.getVRegValue()->getName() << ">";
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O << "<" << MO.getVRegValue()->getName() << ">";
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return;
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default:
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O << "<unknown op ty>"; return;
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@ -145,164 +145,12 @@ static void printMemReference(std::ostream &O, const MachineInstr *MI,
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O << "]";
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}
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static inline void toHexDigit(std::ostream &O, unsigned char V) {
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if (V >= 10)
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O << (char)('A'+V-10);
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else
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O << (char)('0'+V);
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}
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static std::ostream &toHex(std::ostream &O, unsigned char V) {
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toHexDigit(O, V >> 4);
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toHexDigit(O, V & 0xF);
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return O;
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}
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static std::ostream &emitConstant(std::ostream &O, unsigned Val, unsigned Size){
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// Output the constant in little endian byte order...
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for (unsigned i = 0; i != Size; ++i) {
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toHex(O, Val) << " ";
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Val >>= 8;
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}
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return O;
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}
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namespace N86 { // Native X86 Register numbers...
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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// getX86RegNum - This function maps LLVM register identifiers to their X86
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// specific numbering, which is used in various places encoding instructions.
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//
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static unsigned getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
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case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
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case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
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case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
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default:
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assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
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"Unknown physical register!");
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DEBUG(std::cerr << "Register allocator hasn't allocated " << RegNo
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<< " correctly yet!\n");
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return 0;
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}
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}
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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static void emitRegModRMByte(std::ostream &O, unsigned ModRMReg,
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unsigned RegOpcodeField) {
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toHex(O, ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg))) << " ";
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}
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inline static void emitSIBByte(std::ostream &O, unsigned SS, unsigned Index,
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unsigned Base) {
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// SIB byte is in the same format as the ModRMByte...
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toHex(O, ModRMByte(SS, Index, Base));
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}
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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static void emitMemModRMByte(std::ostream &O, const MachineInstr *MI,
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unsigned Op, unsigned RegOpcodeField) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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const MachineOperand &BaseReg = MI->getOperand(Op);
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const MachineOperand &Scale = MI->getOperand(Op+1);
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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const MachineOperand &Disp = MI->getOperand(Op+3);
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// Is a SIB byte needed?
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if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
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if (BaseReg.getReg() == 0) { // Just a displacement?
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// Emit special case [disp32] encoding
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toHex(O, ModRMByte(0, RegOpcodeField, 5));
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emitConstant(O, Disp.getImmedValue(), 4);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
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// Emit simple indirect register encoding... [EAX] f.e.
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toHex(O, ModRMByte(0, RegOpcodeField, BaseRegNo));
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} else if (isDisp8(Disp.getImmedValue())) {
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// Emit the disp8 encoding... [REG+disp8]
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toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(O, Disp.getImmedValue(), 1);
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(O, Disp.getImmedValue(), 4);
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}
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}
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} else { // We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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if (BaseReg.getReg() == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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toHex(O, ModRMByte(0, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (Disp.getImmedValue() == 0) {
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// Emit no displacement ModR/M byte
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toHex(O, ModRMByte(0, RegOpcodeField, 4));
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} else if (isDisp8(Disp.getImmedValue())) {
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// Emit the disp8 encoding...
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toHex(O, ModRMByte(1, RegOpcodeField, 4));
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} else {
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// Emit the normal disp32 encoding...
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toHex(O, ModRMByte(2, RegOpcodeField, 4));
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImmedValue()];
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if (BaseReg.getReg() == 0) {
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// Handle the SIB byte for the case where there is no base. The
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// displacement has already been output.
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assert(IndexReg.getReg() && "Index register must be specified!");
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emitSIBByte(O, SS, getX86RegNum(IndexReg.getReg()), 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
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emitSIBByte(O, SS, IndexRegNo, BaseRegNo);
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}
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// Do we need to output a displacement?
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if (Disp.getImmedValue() != 0 || ForceDisp32) {
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if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
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emitConstant(O, Disp.getImmedValue(), 1);
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else
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emitConstant(O, Disp.getImmedValue(), 4);
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}
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}
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}
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// print - Print out an x86 instruction in intel syntax
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void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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const TargetMachine &TM) const {
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unsigned Opcode = MI->getOpcode();
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const MachineInstrDescriptor &Desc = get(Opcode);
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// Print instruction prefixes if neccesary
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if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
|
||||
if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
|
||||
|
||||
switch (Desc.TSFlags & X86II::FormMask) {
|
||||
case X86II::RawFrm:
|
||||
// The accepted forms of Raw instructions are:
|
||||
@ -312,14 +160,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
assert(MI->getNumOperands() == 0 ||
|
||||
(MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
|
||||
"Illegal raw instruction!");
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
|
||||
if (MI->getNumOperands() == 1) {
|
||||
Value *V = MI->getOperand(0).getVRegValue();
|
||||
emitConstant(O, 0, 4);
|
||||
}
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
|
||||
if (MI->getNumOperands() == 1) {
|
||||
@ -340,14 +180,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
"Illegal form for AddRegFrm instruction!");
|
||||
|
||||
unsigned Reg = MI->getOperand(0).getReg();
|
||||
toHex(O, getBaseOpcodeFor(Opcode) + getX86RegNum(Reg)) << " ";
|
||||
|
||||
if (MI->getNumOperands() == 2) {
|
||||
unsigned Size = 4;
|
||||
emitConstant(O, MI->getOperand(1).getImmedValue(), Size);
|
||||
}
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
if (MI->getNumOperands() == 2) {
|
||||
@ -377,12 +210,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
unsigned ModRMReg = MI->getOperand(0).getReg();
|
||||
unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
|
||||
emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
O << ", ";
|
||||
@ -397,10 +224,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
//
|
||||
assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
|
||||
isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
emitMemModRMByte(O, MI, 0, getX86RegNum(MI->getOperand(4).getReg()));
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " <SIZE> PTR ";
|
||||
printMemReference(O, MI, 0, RI);
|
||||
O << ", ";
|
||||
@ -428,12 +252,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
|
||||
unsigned ExtraReg = MI->getOperand(0).getReg();
|
||||
emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
O << ", ";
|
||||
@ -455,11 +273,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
unsigned ExtraReg = MI->getOperand(0).getReg();
|
||||
emitMemModRMByte(O, MI, MI->getNumOperands()-4, getX86RegNum(ExtraReg));
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
O << ", <SIZE> PTR ";
|
||||
@ -491,17 +304,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
unsigned ExtraField = (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r;
|
||||
emitRegModRMByte(O, MI->getOperand(0).getReg(), ExtraField);
|
||||
|
||||
if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
|
||||
unsigned Size = 4;
|
||||
emitConstant(O, MI->getOperand(MI->getNumOperands()-1).getImmedValue(),
|
||||
Size);
|
||||
}
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
|
||||
|
||||
@ -108,7 +108,7 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
|
||||
O << (int)MO.getImmedValue();
|
||||
return;
|
||||
case MachineOperand::MO_PCRelativeDisp:
|
||||
O << "< " << MO.getVRegValue()->getName() << ">";
|
||||
O << "<" << MO.getVRegValue()->getName() << ">";
|
||||
return;
|
||||
default:
|
||||
O << "<unknown op ty>"; return;
|
||||
@ -145,164 +145,12 @@ static void printMemReference(std::ostream &O, const MachineInstr *MI,
|
||||
O << "]";
|
||||
}
|
||||
|
||||
static inline void toHexDigit(std::ostream &O, unsigned char V) {
|
||||
if (V >= 10)
|
||||
O << (char)('A'+V-10);
|
||||
else
|
||||
O << (char)('0'+V);
|
||||
}
|
||||
|
||||
static std::ostream &toHex(std::ostream &O, unsigned char V) {
|
||||
toHexDigit(O, V >> 4);
|
||||
toHexDigit(O, V & 0xF);
|
||||
return O;
|
||||
}
|
||||
|
||||
static std::ostream &emitConstant(std::ostream &O, unsigned Val, unsigned Size){
|
||||
// Output the constant in little endian byte order...
|
||||
for (unsigned i = 0; i != Size; ++i) {
|
||||
toHex(O, Val) << " ";
|
||||
Val >>= 8;
|
||||
}
|
||||
return O;
|
||||
}
|
||||
|
||||
namespace N86 { // Native X86 Register numbers...
|
||||
enum {
|
||||
EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
// getX86RegNum - This function maps LLVM register identifiers to their X86
|
||||
// specific numbering, which is used in various places encoding instructions.
|
||||
//
|
||||
static unsigned getX86RegNum(unsigned RegNo) {
|
||||
switch(RegNo) {
|
||||
case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
|
||||
case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
|
||||
case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
|
||||
case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
|
||||
case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
|
||||
case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
|
||||
case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
|
||||
case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
|
||||
default:
|
||||
assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
|
||||
"Unknown physical register!");
|
||||
DEBUG(std::cerr << "Register allocator hasn't allocated " << RegNo
|
||||
<< " correctly yet!\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
|
||||
unsigned RM) {
|
||||
assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
|
||||
return RM | (RegOpcode << 3) | (Mod << 6);
|
||||
}
|
||||
|
||||
static void emitRegModRMByte(std::ostream &O, unsigned ModRMReg,
|
||||
unsigned RegOpcodeField) {
|
||||
toHex(O, ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg))) << " ";
|
||||
}
|
||||
|
||||
inline static void emitSIBByte(std::ostream &O, unsigned SS, unsigned Index,
|
||||
unsigned Base) {
|
||||
// SIB byte is in the same format as the ModRMByte...
|
||||
toHex(O, ModRMByte(SS, Index, Base));
|
||||
}
|
||||
|
||||
static bool isDisp8(int Value) {
|
||||
return Value == (signed char)Value;
|
||||
}
|
||||
|
||||
static void emitMemModRMByte(std::ostream &O, const MachineInstr *MI,
|
||||
unsigned Op, unsigned RegOpcodeField) {
|
||||
assert(isMem(MI, Op) && "Invalid memory reference!");
|
||||
const MachineOperand &BaseReg = MI->getOperand(Op);
|
||||
const MachineOperand &Scale = MI->getOperand(Op+1);
|
||||
const MachineOperand &IndexReg = MI->getOperand(Op+2);
|
||||
const MachineOperand &Disp = MI->getOperand(Op+3);
|
||||
|
||||
// Is a SIB byte needed?
|
||||
if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
|
||||
if (BaseReg.getReg() == 0) { // Just a displacement?
|
||||
// Emit special case [disp32] encoding
|
||||
toHex(O, ModRMByte(0, RegOpcodeField, 5));
|
||||
emitConstant(O, Disp.getImmedValue(), 4);
|
||||
} else {
|
||||
unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
|
||||
if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
|
||||
// Emit simple indirect register encoding... [EAX] f.e.
|
||||
toHex(O, ModRMByte(0, RegOpcodeField, BaseRegNo));
|
||||
} else if (isDisp8(Disp.getImmedValue())) {
|
||||
// Emit the disp8 encoding... [REG+disp8]
|
||||
toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
|
||||
emitConstant(O, Disp.getImmedValue(), 1);
|
||||
} else {
|
||||
// Emit the most general non-SIB encoding: [REG+disp32]
|
||||
toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
|
||||
emitConstant(O, Disp.getImmedValue(), 4);
|
||||
}
|
||||
}
|
||||
|
||||
} else { // We need a SIB byte, so start by outputting the ModR/M byte first
|
||||
assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
|
||||
|
||||
bool ForceDisp32 = false;
|
||||
if (BaseReg.getReg() == 0) {
|
||||
// If there is no base register, we emit the special case SIB byte with
|
||||
// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
|
||||
toHex(O, ModRMByte(0, RegOpcodeField, 4));
|
||||
ForceDisp32 = true;
|
||||
} else if (Disp.getImmedValue() == 0) {
|
||||
// Emit no displacement ModR/M byte
|
||||
toHex(O, ModRMByte(0, RegOpcodeField, 4));
|
||||
} else if (isDisp8(Disp.getImmedValue())) {
|
||||
// Emit the disp8 encoding...
|
||||
toHex(O, ModRMByte(1, RegOpcodeField, 4));
|
||||
} else {
|
||||
// Emit the normal disp32 encoding...
|
||||
toHex(O, ModRMByte(2, RegOpcodeField, 4));
|
||||
}
|
||||
|
||||
// Calculate what the SS field value should be...
|
||||
static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
|
||||
unsigned SS = SSTable[Scale.getImmedValue()];
|
||||
|
||||
if (BaseReg.getReg() == 0) {
|
||||
// Handle the SIB byte for the case where there is no base. The
|
||||
// displacement has already been output.
|
||||
assert(IndexReg.getReg() && "Index register must be specified!");
|
||||
emitSIBByte(O, SS, getX86RegNum(IndexReg.getReg()), 5);
|
||||
} else {
|
||||
unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
|
||||
unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
|
||||
emitSIBByte(O, SS, IndexRegNo, BaseRegNo);
|
||||
}
|
||||
|
||||
// Do we need to output a displacement?
|
||||
if (Disp.getImmedValue() != 0 || ForceDisp32) {
|
||||
if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
|
||||
emitConstant(O, Disp.getImmedValue(), 1);
|
||||
else
|
||||
emitConstant(O, Disp.getImmedValue(), 4);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// print - Print out an x86 instruction in intel syntax
|
||||
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
const TargetMachine &TM) const {
|
||||
unsigned Opcode = MI->getOpcode();
|
||||
const MachineInstrDescriptor &Desc = get(Opcode);
|
||||
|
||||
// Print instruction prefixes if neccesary
|
||||
if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
|
||||
if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
|
||||
|
||||
switch (Desc.TSFlags & X86II::FormMask) {
|
||||
case X86II::RawFrm:
|
||||
// The accepted forms of Raw instructions are:
|
||||
@ -312,14 +160,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
assert(MI->getNumOperands() == 0 ||
|
||||
(MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
|
||||
"Illegal raw instruction!");
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
|
||||
if (MI->getNumOperands() == 1) {
|
||||
Value *V = MI->getOperand(0).getVRegValue();
|
||||
emitConstant(O, 0, 4);
|
||||
}
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
|
||||
if (MI->getNumOperands() == 1) {
|
||||
@ -340,14 +180,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
"Illegal form for AddRegFrm instruction!");
|
||||
|
||||
unsigned Reg = MI->getOperand(0).getReg();
|
||||
toHex(O, getBaseOpcodeFor(Opcode) + getX86RegNum(Reg)) << " ";
|
||||
|
||||
if (MI->getNumOperands() == 2) {
|
||||
unsigned Size = 4;
|
||||
emitConstant(O, MI->getOperand(1).getImmedValue(), Size);
|
||||
}
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
if (MI->getNumOperands() == 2) {
|
||||
@ -377,12 +210,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
unsigned ModRMReg = MI->getOperand(0).getReg();
|
||||
unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
|
||||
emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
O << ", ";
|
||||
@ -397,10 +224,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
//
|
||||
assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
|
||||
isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
emitMemModRMByte(O, MI, 0, getX86RegNum(MI->getOperand(4).getReg()));
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " <SIZE> PTR ";
|
||||
printMemReference(O, MI, 0, RI);
|
||||
O << ", ";
|
||||
@ -428,12 +252,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
|
||||
unsigned ExtraReg = MI->getOperand(0).getReg();
|
||||
emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
O << ", ";
|
||||
@ -455,11 +273,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
unsigned ExtraReg = MI->getOperand(0).getReg();
|
||||
emitMemModRMByte(O, MI, MI->getNumOperands()-4, getX86RegNum(ExtraReg));
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
O << ", <SIZE> PTR ";
|
||||
@ -491,17 +304,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
|
||||
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
||||
unsigned ExtraField = (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r;
|
||||
emitRegModRMByte(O, MI->getOperand(0).getReg(), ExtraField);
|
||||
|
||||
if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
|
||||
unsigned Size = 4;
|
||||
emitConstant(O, MI->getOperand(MI->getNumOperands()-1).getImmedValue(),
|
||||
Size);
|
||||
}
|
||||
|
||||
O << "\n\t\t\t\t";
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
|
||||
|
||||
@ -6,24 +6,35 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "X86TargetMachine.h"
|
||||
#include "X86.h"
|
||||
#include "llvm/PassManager.h"
|
||||
#include "llvm/CodeGen/MachineCodeEmitter.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
|
||||
namespace {
|
||||
struct Emitter : public FunctionPass {
|
||||
class Emitter : public FunctionPass {
|
||||
X86TargetMachine &TM;
|
||||
const X86InstrInfo &II;
|
||||
MachineCodeEmitter &MCE;
|
||||
public:
|
||||
|
||||
Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
|
||||
: TM(tm), II(TM.getInstrInfo()), MCE(mce) {}
|
||||
|
||||
bool runOnFunction(Function &F);
|
||||
|
||||
private:
|
||||
void emitBasicBlock(MachineBasicBlock &MBB);
|
||||
void emitInstruction(MachineInstr &MI);
|
||||
|
||||
void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
|
||||
void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
|
||||
void emitConstant(unsigned Val, unsigned Size);
|
||||
|
||||
void emitMemModRMByte(const MachineInstr &MI,
|
||||
unsigned Op, unsigned RegOpcodeField);
|
||||
|
||||
};
|
||||
}
|
||||
|
||||
@ -56,6 +67,141 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
|
||||
emitInstruction(**I);
|
||||
}
|
||||
|
||||
|
||||
namespace N86 { // Native X86 Register numbers...
|
||||
enum {
|
||||
EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
// getX86RegNum - This function maps LLVM register identifiers to their X86
|
||||
// specific numbering, which is used in various places encoding instructions.
|
||||
//
|
||||
static unsigned getX86RegNum(unsigned RegNo) {
|
||||
switch(RegNo) {
|
||||
case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
|
||||
case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
|
||||
case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
|
||||
case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
|
||||
case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
|
||||
case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
|
||||
case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
|
||||
case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
|
||||
default:
|
||||
assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
|
||||
"Unknown physical register!");
|
||||
assert(0 && "Register allocator hasn't allocated reg correctly yet!");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
|
||||
unsigned RM) {
|
||||
assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
|
||||
return RM | (RegOpcode << 3) | (Mod << 6);
|
||||
}
|
||||
|
||||
void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
|
||||
MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
|
||||
}
|
||||
|
||||
void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
|
||||
// SIB byte is in the same format as the ModRMByte...
|
||||
MCE.emitByte(ModRMByte(SS, Index, Base));
|
||||
}
|
||||
|
||||
void Emitter::emitConstant(unsigned Val, unsigned Size) {
|
||||
// Output the constant in little endian byte order...
|
||||
for (unsigned i = 0; i != Size; ++i) {
|
||||
MCE.emitByte(Val & 255);
|
||||
Val >>= 8;
|
||||
}
|
||||
}
|
||||
|
||||
static bool isDisp8(int Value) {
|
||||
return Value == (signed char)Value;
|
||||
}
|
||||
|
||||
void Emitter::emitMemModRMByte(const MachineInstr &MI,
|
||||
unsigned Op, unsigned RegOpcodeField) {
|
||||
const MachineOperand &BaseReg = MI.getOperand(Op);
|
||||
const MachineOperand &Scale = MI.getOperand(Op+1);
|
||||
const MachineOperand &IndexReg = MI.getOperand(Op+2);
|
||||
const MachineOperand &Disp = MI.getOperand(Op+3);
|
||||
|
||||
// Is a SIB byte needed?
|
||||
if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
|
||||
if (BaseReg.getReg() == 0) { // Just a displacement?
|
||||
// Emit special case [disp32] encoding
|
||||
MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
|
||||
emitConstant(Disp.getImmedValue(), 4);
|
||||
} else {
|
||||
unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
|
||||
if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
|
||||
// Emit simple indirect register encoding... [EAX] f.e.
|
||||
MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
|
||||
} else if (isDisp8(Disp.getImmedValue())) {
|
||||
// Emit the disp8 encoding... [REG+disp8]
|
||||
MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
|
||||
emitConstant(Disp.getImmedValue(), 1);
|
||||
} else {
|
||||
// Emit the most general non-SIB encoding: [REG+disp32]
|
||||
MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
|
||||
emitConstant(Disp.getImmedValue(), 4);
|
||||
}
|
||||
}
|
||||
|
||||
} else { // We need a SIB byte, so start by outputting the ModR/M byte first
|
||||
assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
|
||||
|
||||
bool ForceDisp32 = false;
|
||||
if (BaseReg.getReg() == 0) {
|
||||
// If there is no base register, we emit the special case SIB byte with
|
||||
// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
|
||||
MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
|
||||
ForceDisp32 = true;
|
||||
} else if (Disp.getImmedValue() == 0) {
|
||||
// Emit no displacement ModR/M byte
|
||||
MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
|
||||
} else if (isDisp8(Disp.getImmedValue())) {
|
||||
// Emit the disp8 encoding...
|
||||
MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
|
||||
} else {
|
||||
// Emit the normal disp32 encoding...
|
||||
MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
|
||||
}
|
||||
|
||||
// Calculate what the SS field value should be...
|
||||
static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
|
||||
unsigned SS = SSTable[Scale.getImmedValue()];
|
||||
|
||||
if (BaseReg.getReg() == 0) {
|
||||
// Handle the SIB byte for the case where there is no base. The
|
||||
// displacement has already been output.
|
||||
assert(IndexReg.getReg() && "Index register must be specified!");
|
||||
emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
|
||||
} else {
|
||||
unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
|
||||
unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
|
||||
emitSIBByte(SS, IndexRegNo, BaseRegNo);
|
||||
}
|
||||
|
||||
// Do we need to output a displacement?
|
||||
if (Disp.getImmedValue() != 0 || ForceDisp32) {
|
||||
if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
|
||||
emitConstant(Disp.getImmedValue(), 1);
|
||||
else
|
||||
emitConstant(Disp.getImmedValue(), 4);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static bool isImmediate(const MachineOperand &MO) {
|
||||
return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
|
||||
MO.getType() == MachineOperand::MO_UnextendedImmed;
|
||||
}
|
||||
|
||||
void Emitter::emitInstruction(MachineInstr &MI) {
|
||||
unsigned Opcode = MI.getOpcode();
|
||||
const MachineInstrDescriptor &Desc = II.get(Opcode);
|
||||
@ -64,15 +210,57 @@ void Emitter::emitInstruction(MachineInstr &MI) {
|
||||
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
|
||||
if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix
|
||||
|
||||
unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode);
|
||||
switch (Desc.TSFlags & X86II::FormMask) {
|
||||
case X86II::RawFrm:
|
||||
MCE.emitByte(II.getBaseOpcodeFor(Opcode));
|
||||
MCE.emitByte(BaseOpcode);
|
||||
|
||||
if (MI.getNumOperands() == 1) {
|
||||
assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp);
|
||||
MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue());
|
||||
}
|
||||
|
||||
break;
|
||||
case X86II::AddRegFrm:
|
||||
MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
|
||||
if (MI.getNumOperands() == 2) {
|
||||
unsigned Size = 4;
|
||||
emitConstant(MI.getOperand(1).getImmedValue(), Size);
|
||||
}
|
||||
break;
|
||||
case X86II::MRMDestReg:
|
||||
MCE.emitByte(BaseOpcode);
|
||||
emitRegModRMByte(MI.getOperand(0).getReg(),
|
||||
getX86RegNum(MI.getOperand(MI.getNumOperands()-1).getReg()));
|
||||
break;
|
||||
case X86II::MRMDestMem:
|
||||
MCE.emitByte(BaseOpcode);
|
||||
emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
|
||||
break;
|
||||
case X86II::MRMSrcReg:
|
||||
MCE.emitByte(BaseOpcode);
|
||||
emitRegModRMByte(MI.getOperand(MI.getNumOperands()-1).getReg(),
|
||||
getX86RegNum(MI.getOperand(0).getReg()));
|
||||
break;
|
||||
case X86II::MRMSrcMem:
|
||||
MCE.emitByte(BaseOpcode);
|
||||
emitMemModRMByte(MI, MI.getNumOperands()-4,
|
||||
getX86RegNum(MI.getOperand(0).getReg()));
|
||||
break;
|
||||
|
||||
case X86II::MRMS0r: case X86II::MRMS1r:
|
||||
case X86II::MRMS2r: case X86II::MRMS3r:
|
||||
case X86II::MRMS4r: case X86II::MRMS5r:
|
||||
case X86II::MRMS6r: case X86II::MRMS7r:
|
||||
MCE.emitByte(BaseOpcode);
|
||||
emitRegModRMByte(MI.getOperand(0).getReg(),
|
||||
(Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r);
|
||||
|
||||
if (isImmediate(MI.getOperand(MI.getNumOperands()-1))) {
|
||||
unsigned Size = 4;
|
||||
emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user