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[Hexagon] Generate "insert" instructions more aggressively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241681 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -21,6 +21,7 @@ add_llvm_target(HexagonCodeGen
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HexagonExpandPredSpillCode.cpp
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HexagonFixupHwLoops.cpp
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HexagonFrameLowering.cpp
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HexagonGenInsert.cpp
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HexagonHardwareLoops.cpp
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HexagonInstrInfo.cpp
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HexagonISelDAGToDAG.cpp
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1598
lib/Target/Hexagon/HexagonGenInsert.cpp
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1598
lib/Target/Hexagon/HexagonGenInsert.cpp
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File diff suppressed because it is too large
Load Diff
@ -37,6 +37,8 @@ static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
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cl::init(true), cl::Hidden, cl::ZeroOrMore,
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cl::desc("Early expansion of MUX"));
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static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
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cl::Hidden, cl::desc("Generate \"insert\" instructions"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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@ -64,12 +66,12 @@ namespace llvm {
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createHexagonDelaySlotFillerPass(const TargetMachine &TM);
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FunctionPass *createHexagonFPMoverPass(const TargetMachine &TM);
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FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
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FunctionPass *createHexagonCFGOptimizer();
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FunctionPass *createHexagonSplitConst32AndConst64();
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FunctionPass *createHexagonExpandPredSpillCode();
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FunctionPass *createHexagonGenInsert();
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FunctionPass *createHexagonHardwareLoops();
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FunctionPass *createHexagonPeephole();
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FunctionPass *createHexagonFixupHwLoops();
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@ -146,6 +148,8 @@ bool HexagonPassConfig::addInstSelector() {
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if (!NoOpt) {
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addPass(createHexagonPeephole());
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printAndVerify("After hexagon peephole pass");
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if (EnableGenInsert)
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addPass(createHexagonGenInsert(), false);
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}
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return false;
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66
test/CodeGen/Hexagon/insert-basic.ll
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66
test/CodeGen/Hexagon/insert-basic.ll
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@ -0,0 +1,66 @@
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; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
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; CHECK-DAG: insert(r{{[0-9]*}}, #17, #0)
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; CHECK-DAG: insert(r{{[0-9]*}}, #18, #0)
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; CHECK-DAG: insert(r{{[0-9]*}}, #22, #0)
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; CHECK-DAG: insert(r{{[0-9]*}}, #12, #0)
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; C source:
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; typedef struct {
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; unsigned x1:23;
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; unsigned x2:17;
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; unsigned x3:18;
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; unsigned x4:22;
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; unsigned x5:12;
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; } structx_t;
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;
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; void foo(structx_t *px, int y1, int y2, int y3, int y4, int y5) {
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; px->x1 = y1;
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; px->x2 = y2;
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; px->x3 = y3;
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; px->x4 = y4;
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; px->x5 = y5;
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; }
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
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target triple = "hexagon"
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%struct.structx_t = type { [3 x i8], i8, [3 x i8], i8, [3 x i8], i8, [3 x i8], i8, [2 x i8], [2 x i8] }
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define void @foo(%struct.structx_t* nocapture %px, i32 %y1, i32 %y2, i32 %y3, i32 %y4, i32 %y5) nounwind {
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entry:
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%bf.value = and i32 %y1, 8388607
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%0 = bitcast %struct.structx_t* %px to i32*
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%1 = load i32, i32* %0, align 4
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%2 = and i32 %1, -8388608
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%3 = or i32 %2, %bf.value
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store i32 %3, i32* %0, align 4
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%bf.value1 = and i32 %y2, 131071
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%bf.field.offs = getelementptr %struct.structx_t, %struct.structx_t* %px, i32 0, i32 0, i32 4
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%4 = bitcast i8* %bf.field.offs to i32*
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%5 = load i32, i32* %4, align 4
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%6 = and i32 %5, -131072
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%7 = or i32 %6, %bf.value1
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store i32 %7, i32* %4, align 4
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%bf.value2 = and i32 %y3, 262143
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%bf.field.offs3 = getelementptr %struct.structx_t, %struct.structx_t* %px, i32 0, i32 0, i32 8
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%8 = bitcast i8* %bf.field.offs3 to i32*
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%9 = load i32, i32* %8, align 4
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%10 = and i32 %9, -262144
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%11 = or i32 %10, %bf.value2
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store i32 %11, i32* %8, align 4
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%bf.value4 = and i32 %y4, 4194303
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%bf.field.offs5 = getelementptr %struct.structx_t, %struct.structx_t* %px, i32 0, i32 0, i32 12
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%12 = bitcast i8* %bf.field.offs5 to i32*
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%13 = load i32, i32* %12, align 4
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%14 = and i32 %13, -4194304
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%15 = or i32 %14, %bf.value4
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store i32 %15, i32* %12, align 4
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%bf.value6 = and i32 %y5, 4095
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%bf.field.offs7 = getelementptr %struct.structx_t, %struct.structx_t* %px, i32 0, i32 0, i32 16
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%16 = bitcast i8* %bf.field.offs7 to i32*
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%17 = load i32, i32* %16, align 4
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%18 = and i32 %17, -4096
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%19 = or i32 %18, %bf.value6
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store i32 %19, i32* %16, align 4
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ret void
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}
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