From ea2378138fed05c907f698812a06356a5c8fd2ec Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Tue, 11 Mar 2008 07:55:13 +0000
Subject: [PATCH] Use TargetRegisterInfo::getPhysicalRegisterRegClass. Remove
 duplicated code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48221 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/LowerSubregs.cpp | 27 ++++++---------------------
 1 file changed, 6 insertions(+), 21 deletions(-)

diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 232dc061e58..61601d50d05 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -44,21 +44,6 @@ FunctionPass *llvm::createLowerSubregsPass() {
   return new LowerSubregsInstructionPass(); 
 }
 
-// Returns the Register Class of a physical register.
-static const TargetRegisterClass *getPhysicalRegisterRegClass(
-        const TargetRegisterInfo &TRI,
-        unsigned reg) {
-  assert(TargetRegisterInfo::isPhysicalRegister(reg) &&
-         "reg must be a physical register");
-  // Pick the register class of the right type that contains this physreg.
-  for (TargetRegisterInfo::regclass_iterator I = TRI.regclass_begin(),
-         E = TRI.regclass_end(); I != E; ++I)
-    if ((*I)->contains(reg))
-      return *I;
-  assert(false && "Couldn't find the register class");
-  return 0;
-}
-
 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
    MachineBasicBlock *MBB = MI->getParent();
    MachineFunction &MF = *MBB->getParent();
@@ -82,11 +67,11 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
    if (SrcReg != DstReg) {
      const TargetRegisterClass *TRC = 0;
      if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
-       TRC = getPhysicalRegisterRegClass(TRI, DstReg);
+       TRC = TRI.getPhysicalRegisterRegClass(DstReg);
      } else {
        TRC = MF.getRegInfo().getRegClass(DstReg);
      }
-     assert(TRC == getPhysicalRegisterRegClass(TRI, SrcReg) &&
+     assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
              "Extract subreg and Dst must be of same register class");
 
      TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
@@ -155,7 +140,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
       // Insert sub-register copy
       const TargetRegisterClass *TRC1 = 0;
       if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
-        TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
+        TRC1 = TRI.getPhysicalRegisterRegClass(InsReg);
       } else {
         TRC1 = MF.getRegInfo().getRegClass(InsReg);
       }
@@ -179,11 +164,11 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     // Insert super-register copy
     const TargetRegisterClass *TRC0 = 0;
     if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
-      TRC0 = getPhysicalRegisterRegClass(TRI, DstReg);
+      TRC0 = TRI.getPhysicalRegisterRegClass(DstReg);
     } else {
       TRC0 = MF.getRegInfo().getRegClass(DstReg);
     }
-    assert(TRC0 == getPhysicalRegisterRegClass(TRI, SrcReg) &&
+    assert(TRC0 == TRI.getPhysicalRegisterRegClass(SrcReg) &&
             "Insert superreg and Dst must be of same register class");
 
     TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
@@ -204,7 +189,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     // Insert sub-register copy
     const TargetRegisterClass *TRC1 = 0;
     if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
-      TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
+      TRC1 = TRI.getPhysicalRegisterRegClass(InsReg);
     } else {
       TRC1 = MF.getRegInfo().getRegClass(InsReg);
     }