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Remove SIL, DIL, and BPL from the GR8_NOREX allocation order also.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94560 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-01-26 18:30:24 +00:00
parent 369d4b4c2e
commit ea32d8f465
1 changed files with 5 additions and 11 deletions
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16
lib/Target/X86/X86RegisterInfo.td
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@ -520,8 +520,9 @@ def GR8_NOREX : RegisterClass<"X86", [i8], 8,
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
// In 64-bit mode, it's not safe to blindly allocate H registers.
static const unsigned X86_GR8_NOREX_AO_64[] = {
X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL, X86::BPL
X86::AL, X86::CL, X86::DL, X86::BL
};
GR8_NOREXClass::iterator
@ -537,18 +538,11 @@ def GR8_NOREX : RegisterClass<"X86", [i8], 8,
GR8_NOREXClass::iterator
GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
// Does the function dedicate RBP / EBP to being a frame ptr?
if (!Subtarget.is64Bit())
// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
return begin() + 8;
else if (RI->hasFP(MF))
// If so, don't allocate SPL or BPL.
return array_endof(X86_GR8_NOREX_AO_64) - 1;
else
// If not, just don't allocate SPL.
if (Subtarget.is64Bit())
return array_endof(X86_GR8_NOREX_AO_64);
else
return end();
}
}];
}