From ea54c9846b2973cafa8ffd40626f5676ba9ccfee Mon Sep 17 00:00:00 2001 From: Anton Korobeynikov Date: Sun, 3 May 2009 13:13:17 +0000 Subject: [PATCH] Add left shift git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70747 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/MSP430/MSP430ISelLowering.cpp | 12 +++++++++--- lib/Target/MSP430/MSP430ISelLowering.h | 4 ++-- lib/Target/MSP430/MSP430InstrInfo.td | 6 ++++++ 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index 5e67265487c..6cc5cd9ebe2 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -68,6 +68,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) : setTruncStoreAction(MVT::i16, MVT::i8, Expand); setOperationAction(ISD::SRA, MVT::i16, Custom); + setOperationAction(ISD::SHL, MVT::i16, Custom); setOperationAction(ISD::RET, MVT::Other, Custom); setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); setOperationAction(ISD::BR_CC, MVT::Other, Expand); @@ -82,6 +83,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) : SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); + case ISD::SHL: // FALLTHROUGH case ISD::SRA: return LowerShifts(Op, DAG); case ISD::RET: return LowerRET(Op, DAG); case ISD::CALL: return LowerCALL(Op, DAG); @@ -416,12 +418,14 @@ MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, SDValue MSP430TargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) { - assert(Op.getOpcode() == ISD::SRA && "Only SRA is currently supported."); + unsigned Opc = Op.getOpcode(); + assert((Opc == ISD::SRA || ISD::SHL) && + "Only SRA and SHL are currently supported."); SDNode* N = Op.getNode(); MVT VT = Op.getValueType(); DebugLoc dl = N->getDebugLoc(); - // We currently only lower SRA of constant argument. + // We currently only lower shifts of constant argument. if (!isa(N->getOperand(1))) return SDValue(); @@ -432,7 +436,8 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op, // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N SDValue Victim = N->getOperand(0); while (ShiftAmount--) - Victim = DAG.getNode(MSP430ISD::RRA, dl, VT, Victim); + Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA), + dl, VT, Victim); return Victim; } @@ -560,6 +565,7 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const { default: return NULL; case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; case MSP430ISD::RRA: return "MSP430ISD::RRA"; + case MSP430ISD::RLA: return "MSP430ISD::RRA"; case MSP430ISD::CALL: return "MSP430ISD::CALL"; case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; case MSP430ISD::BRCOND: return "MSP430ISD::BRCOND"; diff --git a/lib/Target/MSP430/MSP430ISelLowering.h b/lib/Target/MSP430/MSP430ISelLowering.h index f14af1d52ca..d6739cb78b8 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.h +++ b/lib/Target/MSP430/MSP430ISelLowering.h @@ -27,8 +27,8 @@ namespace llvm { /// Return with a flag operand. Operand 0 is the chain operand. RET_FLAG, - /// Y = RRA X, rotate right arithmetically - RRA, + /// Y = R{R,L}A X, rotate right (left) arithmetically + RRA, RLA, /// CALL/TAILCALL - These operations represent an abstract call /// instruction, which includes a bunch of information. diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td index 2615869dd9f..8b3e4e43050 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.td +++ b/lib/Target/MSP430/MSP430InstrInfo.td @@ -41,6 +41,7 @@ def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInFlag]>; def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>; +def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>; def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call, [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; @@ -591,6 +592,11 @@ def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src), [(set GR16:$dst, (MSP430rra GR16:$src)), (implicit SRW)]>; +def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src), + "rla.w\t$dst", + [(set GR16:$dst, (MSP430rla GR16:$src)), + (implicit SRW)]>; + def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src), "sxt\t$dst", [(set GR16:$dst, (sext_inreg GR16:$src, i8)),