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Remove the ZERO_EXTEND_INREG node which is redundant with AND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21263 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -141,13 +141,12 @@ namespace ISD {
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SINT_TO_FP,
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SINT_TO_FP,
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UINT_TO_FP,
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UINT_TO_FP,
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// SIGN_EXTEND_INREG/ZERO_EXTEND_INREG - These operators atomically performs
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// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
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// a SHL/(SRA|SHL) pair to (sign|zero) extend a small value in a large
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// sign extend a small value in a large integer register (e.g. sign
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// integer register (e.g. sign extending the low 8 bits of a 32-bit register
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// extending the low 8 bits of a 32-bit register to fill the top 24 bits
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// to fill the top 24 bits with the 7th bit). The size of the smaller type
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// with the 7th bit). The size of the smaller type is indicated by the
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// is indicated by the ExtraValueType in the MVTSDNode for the operator.
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// ExtraValueType in the MVTSDNode for the operator.
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SIGN_EXTEND_INREG,
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SIGN_EXTEND_INREG,
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ZERO_EXTEND_INREG,
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// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
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// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
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// integer.
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// integer.
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@ -809,7 +808,6 @@ public:
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static bool classof(const SDNode *N) {
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static bool classof(const SDNode *N) {
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return
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return
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N->getOpcode() == ISD::SIGN_EXTEND_INREG ||
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N->getOpcode() == ISD::SIGN_EXTEND_INREG ||
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N->getOpcode() == ISD::ZERO_EXTEND_INREG ||
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N->getOpcode() == ISD::FP_ROUND_INREG ||
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N->getOpcode() == ISD::FP_ROUND_INREG ||
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N->getOpcode() == ISD::EXTLOAD ||
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N->getOpcode() == ISD::EXTLOAD ||
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N->getOpcode() == ISD::SEXTLOAD ||
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N->getOpcode() == ISD::SEXTLOAD ||
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