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load f64 +0.0 in a cleaner way. This fix part of PR5445

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93876 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-01-19 12:53:04 +00:00
parent e5ebd5f2ae
commit ea98278935
2 changed files with 12 additions and 12 deletions
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15
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -461,9 +461,18 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
case ISD::ConstantFP: { case ISD::ConstantFP: {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node); ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32); SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
ReplaceUses(SDValue(Node, 0), Zero); Mips::ZERO, MVT::i32);
return Zero.getNode(); SDValue Undef = SDValue(
CurDAG->getMachineNode(
TargetInstrInfo::IMPLICIT_DEF, dl, MVT::f64), 0);
SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl,
MVT::f64, Undef, SDValue(MTC, 0));
SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl,
MVT::f64, I0, SDValue(MTC, 0));
ReplaceUses(SDValue(Node, 0), I1);
return I1.getNode();
} }
break; break;
} }

9
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -134,8 +134,6 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *DestRC, const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const { const TargetRegisterClass *SrcRC) const {
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
const MachineFunction *MF = MBB.getParent();
const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
@ -156,13 +154,6 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
else if ((DestRC == Mips::FGR32RegisterClass) && else if ((DestRC == Mips::FGR32RegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass)) (SrcRC == Mips::CPURegsRegisterClass))
BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg); BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
else if ((DestRC == Mips::AFGR64RegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass) &&
(SrcReg == Mips::ZERO)) {
const unsigned *AliasSet = TRI->getAliasSet(DestReg);
BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[0]).addReg(SrcReg);
BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[1]).addReg(SrcReg);
}
// Move from/to Hi/Lo registers // Move from/to Hi/Lo registers
else if ((DestRC == Mips::HILORegisterClass) && else if ((DestRC == Mips::HILORegisterClass) &&