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https://github.com/c64scene-ar/llvm-6502.git
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Add a catch-all WriteSystem SchedWrite type.
This is used for all the expensive system instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177598 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5402,6 +5402,7 @@ def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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// SSSE3 - Thread synchronization
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//===---------------------------------------------------------------------===//
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let SchedRW = [WriteSystem] in {
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let usesCustomInserter = 1 in {
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def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
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[(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
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@ -5415,6 +5416,7 @@ let Uses = [ECX, EAX] in
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def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
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[(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
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TB, Requires<[HasSSE3]>;
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} // SchedRW
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def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
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def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
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@ -13,6 +13,7 @@
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//
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//===----------------------------------------------------------------------===//
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let SchedRW = [WriteSystem] in {
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let Defs = [RAX, RDX] in
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def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
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TB;
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@ -35,6 +36,7 @@ let Uses = [EFLAGS] in
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def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
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def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
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[(int_x86_int (i8 3))], IIC_INT3>;
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} // SchedRW
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def : Pat<(debugtrap),
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(INT3)>;
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@ -43,6 +45,7 @@ def : Pat<(debugtrap),
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// FIXME: This doesn't work because InstAlias can't match immediate constants.
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//def : InstAlias<"int\t$3", (INT3)>;
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let SchedRW = [WriteSystem] in {
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def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
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[(int_x86_int imm:$trap)], IIC_INT>;
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@ -65,11 +68,13 @@ def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
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def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>;
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def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
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Requires<[In64BitMode]>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Input/Output Instructions.
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//
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let SchedRW = [WriteSystem] in {
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let Defs = [AL], Uses = [DX] in
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def IN8rr : I<0xEC, RawFrm, (outs), (ins),
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"in{b}\t{%dx, %al|AL, DX}", [], IIC_IN_RR>;
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@ -113,10 +118,12 @@ def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
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def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
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def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
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def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Moves to and from debug registers
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let SchedRW = [WriteSystem] in {
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def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB;
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def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
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@ -126,10 +133,12 @@ def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB;
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def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Moves to and from control registers
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let SchedRW = [WriteSystem] in {
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def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB;
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def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
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@ -139,6 +148,7 @@ def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB;
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def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Segment override instruction prefixes
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@ -155,6 +165,7 @@ def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
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// Moves to and from segment registers.
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//
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let SchedRW = [WriteMove] in {
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def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
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def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
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@ -182,10 +193,12 @@ def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
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def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Segmentation support instructions.
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let SchedRW = [WriteSystem] in {
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def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
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def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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@ -347,10 +360,12 @@ def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
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"verw\t$seg", [], IIC_VERW_MEM>, TB;
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def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
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"verw\t$seg", [], IIC_VERW_REG>, TB;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Descriptor-table support instructions
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let SchedRW = [WriteSystem] in {
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def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
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"sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[In32BitMode]>;
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def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
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@ -385,9 +400,11 @@ def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
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"lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
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def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
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"lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Specialized register support
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let SchedRW = [WriteSystem] in {
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def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
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def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
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def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
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@ -410,14 +427,18 @@ def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
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"lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
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def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Cache instructions
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let SchedRW = [WriteSystem] in {
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def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
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def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// XSAVE instructions
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let SchedRW = [WriteSystem] in {
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let Defs = [RDX, RAX], Uses = [RCX] in
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def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
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@ -438,6 +459,7 @@ let Uses = [RDX, RAX] in {
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def XSAVEOPT64 : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
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"xsaveoptq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
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}
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// VIA PadLock crypto instructions
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@ -83,6 +83,9 @@ defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer.
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defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float.
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defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion.
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// Catch-all for expensive system instructions.
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def WriteSystem : SchedWrite;
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for X86
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def IIC_DEFAULT : InstrItinClass;
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