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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166780 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -205,6 +205,11 @@ class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
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class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
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class FRR16_M_ins<bits<5> f, string asmstr,
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InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins),
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@ -600,14 +605,14 @@ def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
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// Purpose: Negate
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// To negate an integer value.
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//
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def NegRxRy16: FRR16_ins<0b11101, "neg", IIAlu>;
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def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
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//
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// Format: NOT rx, ry MIPS16e
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// Purpose: Not
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// To complement an integer value
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//
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def NotRxRy16: FRR16_ins<0b01111, "not", IIAlu>;
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def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
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//
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// Format: OR rx, ry MIPS16e
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