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ARM: mark various aliases with their architecture requirements.

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If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.

This tidies up the obvious VFP and NEON cases I found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193340 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2013-10-24 12:22:58 +00:00
parent ef713e27b1
commit eac623a18b
4 changed files with 36 additions and 8 deletions
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8
lib/Target/ARM/ARMInstrNEON.td
View File

@ -5158,10 +5158,10 @@ def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
// Vector Move Operations.
// VMOV : Vector Move (Register)
def : InstAlias<"vmov${p} $Vd, $Vm",
(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
def : InstAlias<"vmov${p} $Vd, $Vm",
(VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vmov${p} $Vd, $Vm",
(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vmov${p} $Vd, $Vm",
(VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
// VMOV : Vector Move (Immediate)

12
lib/Target/ARM/ARMInstrVFP.td
View File

@ -671,9 +671,11 @@ multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
}
def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
(!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>;
(!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
Requires<[HasFPARMv8]>;
def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
(!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>;
(!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
Requires<[HasFPARMv8]>;
}
defm VRINTZ : vrint_inst_zrx<"z", 0, 1>;
@ -697,9 +699,11 @@ multiclass vrint_inst_anpm<string opc, bits<2> rm> {
}
def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
(!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>;
(!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
Requires<[HasFPARMv8]>;
def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
(!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
(!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
Requires<[HasFPARMv8]>;
}
defm VRINTA : vrint_inst_anpm<"a", 0b00>;

7
test/MC/ARM/diagnostics-noneon.s Normal file
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@ -0,0 +1,7 @@
@ RUN: not llvm-mc -triple=armv7-apple-darwin -mattr=-neon < %s 2> %t
@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
vmov d5, d10
vmov q4, q5
@ CHECK-ERRORS: error: instruction requires: NEON
@ CHECK-ERRORS: error: instruction requires: NEON

17
test/MC/ARM/diagnostics.s
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@ -438,3 +438,20 @@
@ CHECK-ERRORS: error: writeback register not allowed in register list
@ CHECK-ERRORS: error: writeback register not allowed in register list
@ CHECK-ERRORS: error: writeback register not allowed in register list
vrintz.f32.f32 s0, s1
vrintr.f32 s0, s1
vrintx.f64.f64 d2, d5
vrintz.f64 d10, d9
vrinta.f32.f32 s6, s7
vrintn.f32 s8, s9
vrintp.f64.f64 d10, d11
vrintm.f64 d12, d13
@ CHECK-ERRORS: error: instruction requires: FPARMv8
@ CHECK-ERRORS: error: instruction requires: FPARMv8
@ CHECK-ERRORS: error: instruction requires: FPARMv8
@ CHECK-ERRORS: error: instruction requires: FPARMv8
@ CHECK-ERRORS: error: instruction requires: FPARMv8
@ CHECK-ERRORS: error: instruction requires: FPARMv8
@ CHECK-ERRORS: error: instruction requires: FPARMv8
@ CHECK-ERRORS: error: instruction requires: FPARMv8