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https://github.com/c64scene-ar/llvm-6502.git
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Use readsWritesVirtualRegister instead of counting uses and defs when inserting
spills and reloads. This means that a partial define of a register causes a reload so the other parts of the register are preserved. The reload can be prevented by adding an <imp-def> operand for the full register. This is already done by the coalescer and live interval analysis where relevant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105369 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1098,7 +1098,6 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
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if (!mop.isReg())
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if (!mop.isReg())
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continue;
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continue;
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unsigned Reg = mop.getReg();
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unsigned Reg = mop.getReg();
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unsigned RegI = Reg;
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if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
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if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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continue;
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if (Reg != li.reg)
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if (Reg != li.reg)
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@@ -1140,26 +1139,8 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
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//
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//
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// Keep track of whether we replace a use and/or def so that we can
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// Keep track of whether we replace a use and/or def so that we can
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// create the spill interval with the appropriate range.
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// create the spill interval with the appropriate range.
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HasUse = mop.isUse();
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HasDef = mop.isDef();
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SmallVector<unsigned, 2> Ops;
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SmallVector<unsigned, 2> Ops;
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Ops.push_back(i);
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tie(HasUse, HasDef) = MI->readsWritesVirtualRegister(Reg, &Ops);
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for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
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const MachineOperand &MOj = MI->getOperand(j);
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if (!MOj.isReg())
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continue;
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unsigned RegJ = MOj.getReg();
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if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ))
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continue;
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if (RegJ == RegI) {
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Ops.push_back(j);
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if (!MOj.isUndef()) {
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HasUse |= MOj.isUse();
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HasDef |= MOj.isDef();
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}
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}
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}
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// Create a new virtual register for the spill interval.
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// Create a new virtual register for the spill interval.
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// Create the new register now so we can map the fold instruction
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// Create the new register now so we can map the fold instruction
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@@ -1312,10 +1293,7 @@ namespace {
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struct RewriteInfo {
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struct RewriteInfo {
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SlotIndex Index;
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SlotIndex Index;
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MachineInstr *MI;
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MachineInstr *MI;
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bool HasUse;
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RewriteInfo(SlotIndex i, MachineInstr *mi) : Index(i), MI(mi) {}
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bool HasDef;
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RewriteInfo(SlotIndex i, MachineInstr *mi, bool u, bool d)
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: Index(i), MI(mi), HasUse(u), HasDef(d) {}
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};
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};
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struct RewriteInfoCompare {
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struct RewriteInfoCompare {
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@@ -1394,7 +1372,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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// easily see a situation where both registers are reloaded before
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// easily see a situation where both registers are reloaded before
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// the INSERT_SUBREG and both target registers that would overlap.
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// the INSERT_SUBREG and both target registers that would overlap.
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continue;
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continue;
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RewriteMIs.push_back(RewriteInfo(index, MI, O.isUse(), O.isDef()));
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RewriteMIs.push_back(RewriteInfo(index, MI));
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}
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}
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std::sort(RewriteMIs.begin(), RewriteMIs.end(), RewriteInfoCompare());
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std::sort(RewriteMIs.begin(), RewriteMIs.end(), RewriteInfoCompare());
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@@ -1404,18 +1382,11 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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RewriteInfo &rwi = RewriteMIs[i];
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RewriteInfo &rwi = RewriteMIs[i];
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++i;
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++i;
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SlotIndex index = rwi.Index;
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SlotIndex index = rwi.Index;
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bool MIHasUse = rwi.HasUse;
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bool MIHasDef = rwi.HasDef;
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MachineInstr *MI = rwi.MI;
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MachineInstr *MI = rwi.MI;
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// If MI def and/or use the same register multiple times, then there
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// If MI def and/or use the same register multiple times, then there
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// are multiple entries.
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// are multiple entries.
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unsigned NumUses = MIHasUse;
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while (i != e && RewriteMIs[i].MI == MI) {
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while (i != e && RewriteMIs[i].MI == MI) {
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assert(RewriteMIs[i].Index == index);
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assert(RewriteMIs[i].Index == index);
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bool isUse = RewriteMIs[i].HasUse;
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if (isUse) ++NumUses;
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MIHasUse |= isUse;
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MIHasDef |= RewriteMIs[i].HasDef;
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++i;
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++i;
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}
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}
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MachineBasicBlock *MBB = MI->getParent();
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MachineBasicBlock *MBB = MI->getParent();
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@@ -1440,7 +1411,8 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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// = use
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// = use
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// It's better to start a new interval to avoid artifically
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// It's better to start a new interval to avoid artifically
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// extend the new interval.
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// extend the new interval.
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if (MIHasDef && !MIHasUse) {
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if (MI->readsWritesVirtualRegister(li.reg) ==
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std::make_pair(false,true)) {
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MBBVRegsMap.erase(MBB->getNumber());
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MBBVRegsMap.erase(MBB->getNumber());
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ThisVReg = 0;
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ThisVReg = 0;
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}
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}
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@@ -1674,19 +1646,9 @@ addIntervalsForSpillsFast(const LiveInterval &li,
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MachineInstr* MI = &*RI;
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MachineInstr* MI = &*RI;
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SmallVector<unsigned, 2> Indices;
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SmallVector<unsigned, 2> Indices;
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bool HasUse = false;
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bool HasUse, HasDef;
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bool HasDef = false;
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tie(HasUse, HasDef) = MI->readsWritesVirtualRegister(li.reg, &Indices);
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for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
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MachineOperand& mop = MI->getOperand(i);
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if (!mop.isReg() || mop.getReg() != li.reg) continue;
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HasUse |= MI->getOperand(i).isUse();
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HasDef |= MI->getOperand(i).isDef();
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Indices.push_back(i);
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}
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if (!tryFoldMemoryOperand(MI, vrm, NULL, getInstructionIndex(MI),
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if (!tryFoldMemoryOperand(MI, vrm, NULL, getInstructionIndex(MI),
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Indices, true, slot, li.reg)) {
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Indices, true, slot, li.reg)) {
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unsigned NewVReg = mri_->createVirtualRegister(rc);
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unsigned NewVReg = mri_->createVirtualRegister(rc);
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