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Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between

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BL_pred and BLr9_pred.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85297 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2009-10-27 20:45:15 +00:00
parent 98eef869ae
commit eadeffb306
1 changed files with 6 additions and 2 deletions
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8
lib/Target/ARM/ARMInstrInfo.td
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@ -675,7 +675,9 @@ let isCall = 1,
def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl\t${func:call}", IIC_Br, "bl\t${func:call}",
[(ARMcall tglobaladdr:$func)]>, [(ARMcall tglobaladdr:$func)]>,
Requires<[IsARM, IsNotDarwin]>; Requires<[IsARM, IsNotDarwin]> {
let Inst{31-28} = 0b1110;
}
def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl", "\t${func:call}", IIC_Br, "bl", "\t${func:call}",
@ -711,7 +713,9 @@ let isCall = 1,
D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl\t${func:call}", IIC_Br, "bl\t${func:call}",
[(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>; [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
let Inst{31-28} = 0b1110;
}
def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl", "\t${func:call}", IIC_Br, "bl", "\t${func:call}",