From eaeda56649052fc75e527b37089d6d67c4a5976d Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 8 May 2006 20:59:41 +0000 Subject: [PATCH] Implement and_sext.ll:test3, generating: _test4: srawi r3, r3, 16 blr instead of: _test4: srwi r2, r3, 16 extsh r3, r2 blr for: short test4(unsigned X) { return (X >> 16); } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28174 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index e90f902736f..1515df5fd4e 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1936,7 +1936,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { unsigned EVTBits = MVT::getSizeInBits(EVT); // fold (sext_in_reg c1) -> c1 - if (isa(N0)) + if (isa(N0) || N0.getOpcode() == ISD::UNDEF) return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); // If the input is already sign extended, just drop the extension. @@ -1949,6 +1949,13 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); } + // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 + if (N0.getOpcode() == ISD::SRL) { + if (ConstantSDNode *ShAmt = dyn_cast(N0.getOperand(1))) + if (ShAmt->getValue()+EVTBits == MVT::getSizeInBits(VT)) + return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); + } + // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) return DAG.getZeroExtendInReg(N0, EVT);