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Move the ARM SSAT and USAT optional shift amount operand out of the

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instruction opcode.  This also fixes part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2010-08-11 23:10:46 +00:00
parent d29583bd32
commit eaf1c98a7c
9 changed files with 80 additions and 44 deletions
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17
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -1466,9 +1466,7 @@ static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
decodeRd(insn))));
unsigned Pos = slice(insn, 20, 16);
if (Opcode == ARM::SSATlsl ||
Opcode == ARM::SSATasr ||
Opcode == ARM::SSAT16)
if (Opcode == ARM::SSAT || Opcode == ARM::SSAT16)
Pos += 1;
MI.addOperand(MCOperand::CreateImm(Pos));
@ -1476,12 +1474,17 @@ static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
decodeRm(insn))));
if (NumOpsAdded == 4) {
ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl);
// Inst{11-7} encodes the imm5 shift amount.
unsigned ShAmt = slice(insn, 11, 7);
// A8.6.183. Possible ASR shift amount of 32...
if ((Opcode == ARM::SSATasr || Opcode == ARM::USATasr) && ShAmt == 0)
ShAmt = 32;
MI.addOperand(MCOperand::CreateImm(ShAmt));
if (ShAmt == 0) {
// A8.6.183. Possible ASR shift amount of 32...
if (Opc == ARM_AM::asr)
ShAmt = 32;
else
Opc = ARM_AM::no_shift;
}
MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
}
return true;
}