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The most significant encoding bit of GPR:$src or GPR:$dst was over-specified in

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the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch).  Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93759 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-01-18 20:15:56 +00:00
parent 3482c8003a
commit eb231ce51d
1 changed files with 5 additions and 5 deletions
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10
lib/Target/ARM/ARMInstrThumb.td
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@ -208,7 +208,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
[(brind GPR:$dst)]>,
T1Special<{1,0,1,1}> {
T1Special<{1,0,1,?}> {
// <Rd> = Inst{7:2-0} = pc
let Inst{2-0} = 0b111;
}
@ -630,13 +630,13 @@ def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
// FIXME: Make these predicable.
def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
"mov\t$dst, $src", []>,
T1Special<{1,0,0,1}>;
T1Special<{1,0,0,?}>;
def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
"mov\t$dst, $src", []>,
T1Special<{1,0,1,0}>;
T1Special<{1,0,?,0}>;
def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
"mov\t$dst, $src", []>,
T1Special<{1,0,1,1}>;
T1Special<{1,0,?,?}>;
} // neverHasSideEffects
// multiply register
@ -771,7 +771,7 @@ let usesCustomInserter = 1 in // Expanded after instruction selection.
// 16-bit movcc in IT blocks for Thumb2.
def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
"mov", "\t$dst, $rhs", []>,
T1Special<{1,0,1,1}>;
T1Special<{1,0,?,?}>;
def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
"mov", "\t$dst, $rhs", []>,