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[SystemZ] Add GRH32 for the high word of a GR64

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The only thing this does on its own is make the definitions of RISB[HL]G
a bit more precise.  Those instructions are only used by the MC layer at
the moment, so no behavioral change is intended.  The class is needed by
later patches though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191660 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-09-30 10:45:16 +00:00
parent 745ca1eed7
commit eb2f72f454
6 changed files with 38 additions and 14 deletions
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6
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
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@ -32,6 +32,7 @@ static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
namespace {
enum RegisterKind {
GR32Reg,
GRH32Reg,
GR64Reg,
GR128Reg,
ADDR32Reg,
@ -262,6 +263,7 @@ public:
// Used by the TableGen code to check for particular operand types.
bool isGR32() const { return isReg(GR32Reg); }
bool isGRH32() const { return isReg(GRH32Reg); }
bool isGR64() const { return isReg(GR64Reg); }
bool isGR128() const { return isReg(GR128Reg); }
bool isADDR32() const { return isReg(ADDR32Reg); }
@ -356,6 +358,10 @@ public:
return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
}
OperandMatchResultTy
parseGRH32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
}
OperandMatchResultTy
parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
}

6
lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
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@ -66,6 +66,12 @@ static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs);
}
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs);
}
static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {

7
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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@ -34,6 +34,13 @@ const unsigned SystemZMC::GR32Regs[16] = {
SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L
};
const unsigned SystemZMC::GRH32Regs[16] = {
SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H
};
const unsigned SystemZMC::GR64Regs[16] = {
SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,

1
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
View File

@ -42,6 +42,7 @@ namespace SystemZMC {
// as %r0-%r15. It seems better to provide the same interface for
// all classes though.
extern const unsigned GR32Regs[16];
extern const unsigned GRH32Regs[16];
extern const unsigned GR64Regs[16];
extern const unsigned GR128Regs[16];
extern const unsigned FP32Regs[16];

4
lib/Target/SystemZ/SystemZInstrInfo.td
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@ -928,9 +928,9 @@ let Defs = [CC] in {
let isCodeGenOnly = 1 in
def RISBLG32 : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR32>,
Requires<[FeatureHighWord]>;
def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>,
def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>,
Requires<[FeatureHighWord]>;
def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>,
def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>,
Requires<[FeatureHighWord]>;
// Rotate second operand left and perform a logical operation with selected

28
lib/Target/SystemZ/SystemZRegisterInfo.td
View File

@ -56,15 +56,15 @@ class GPR32<bits<16> num, string n> : SystemZReg<n> {
}
// One of the 16 64-bit general-purpose registers.
class GPR64<bits<16> num, string n, GPR32 low>
: SystemZRegWithSubregs<n, [low]> {
class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
: SystemZRegWithSubregs<n, [low, high]> {
let HWEncoding = num;
let SubRegIndices = [subreg_l32];
let SubRegIndices = [subreg_l32, subreg_h32];
}
// 8 even-odd pairs of GPR64s.
class GPR128<bits<16> num, string n, GPR64 high, GPR64 low>
: SystemZRegWithSubregs<n, [high, low]> {
class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>
: SystemZRegWithSubregs<n, [low, high]> {
let HWEncoding = num;
let SubRegIndices = [subreg_l64, subreg_h64];
}
@ -72,7 +72,9 @@ class GPR128<bits<16> num, string n, GPR64 high, GPR64 low>
// General-purpose registers
foreach I = 0-15 in {
def R#I#L : GPR32<I, "r"#I>;
def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L")>, DwarfRegNum<[I]>;
def R#I#H : GPR32<I, "r"#I>;
def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
DwarfRegNum<[I]>;
}
foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
@ -82,10 +84,12 @@ foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
/// Allocate the callee-saved R6-R13 backwards. That way they can be saved
/// together with R14 and R15 in one prolog instruction.
defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uL", 0, 5),
(sequence "R%uL", 15, 6))>;
defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5),
(sequence "R%uD", 15, 6))>;
defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uL", 0, 5),
(sequence "R%uL", 15, 6))>;
defm GRH32 : SystemZRegClass<"GRH32", i32, 32, (add (sequence "R%uH", 0, 5),
(sequence "R%uH", 15, 6))>;
defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5),
(sequence "R%uD", 15, 6))>;
// The architecture doesn't really have any i128 support, so model the
// register pairs as untyped instead.
@ -119,8 +123,8 @@ class FPR64<bits<16> num, string n, FPR32 low>
}
// 8 pairs of FPR64s, with a one-register gap inbetween.
class FPR128<bits<16> num, string n, FPR64 high, FPR64 low>
: SystemZRegWithSubregs<n, [high, low]> {
class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
: SystemZRegWithSubregs<n, [low, high]> {
let HWEncoding = num;
let SubRegIndices = [subreg_l64, subreg_h64];
}