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Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85281 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -325,12 +325,11 @@ public:
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/// scalarizing vs using the wider vector type.
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/// scalarizing vs using the wider vector type.
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virtual EVT getWidenVectorType(EVT VT) const;
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virtual EVT getWidenVectorType(EVT VT) const;
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typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
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/// isFPImmLegal - Returns true if the target can instruction select the
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legal_fpimm_iterator legal_fpimm_begin() const {
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/// specified FP immediate natively. If false, the legalizer will materialize
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return LegalFPImmediates.begin();
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/// the FP immediate as a load from a constant pool.
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}
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virtual bool isFPImmLegal(const APFloat &Imm) const {
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legal_fpimm_iterator legal_fpimm_end() const {
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return false;
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return LegalFPImmediates.end();
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}
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}
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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@ -1051,12 +1050,6 @@ protected:
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PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
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PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
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}
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}
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/// addLegalFPImmediate - Indicate that this target can instruction select
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/// the specified FP immediate natively.
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void addLegalFPImmediate(const APFloat& Imm) {
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LegalFPImmediates.push_back(Imm);
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}
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/// setTargetDAGCombine - Targets should invoke this method for each target
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/// setTargetDAGCombine - Targets should invoke this method for each target
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/// independent node that they want to provide a custom DAG combiner for by
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/// independent node that they want to provide a custom DAG combiner for by
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/// implementing the PerformDAGCombine virtual method.
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/// implementing the PerformDAGCombine virtual method.
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@ -1696,8 +1689,6 @@ private:
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ValueTypeActionImpl ValueTypeActions;
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ValueTypeActionImpl ValueTypeActions;
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std::vector<APFloat> LegalFPImmediates;
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std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
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std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
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/// TargetDAGCombineArray - Targets can specify ISD nodes that they would
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/// TargetDAGCombineArray - Targets can specify ISD nodes that they would
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@ -2573,16 +2573,8 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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case ISD::ConstantFP: {
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case ISD::ConstantFP: {
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ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
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ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
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// Check to see if this FP immediate is already legal.
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// Check to see if this FP immediate is already legal.
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bool isLegal = false;
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for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
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E = TLI.legal_fpimm_end(); I != E; ++I) {
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if (CFP->isExactlyValue(*I)) {
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isLegal = true;
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break;
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}
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}
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// If this is a legal constant, turn it into a TargetConstantFP node.
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// If this is a legal constant, turn it into a TargetConstantFP node.
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if (isLegal)
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if (TLI.isFPImmLegal(CFP->getValueAPF()))
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Results.push_back(SDValue(Node, 0));
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Results.push_back(SDValue(Node, 0));
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else
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else
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Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
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Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
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@ -481,7 +481,7 @@ TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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// ConstantFP nodes default to expand. Targets can either change this to
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// ConstantFP nodes default to expand. Targets can either change this to
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// Legal, in which case all fp constants are legal, or use addLegalFPImmediate
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// Legal, in which case all fp constants are legal, or use isFPImmLegal()
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// to optimize expansions for certain constants.
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// to optimize expansions for certain constants.
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setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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@ -157,11 +157,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
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setStackPointerRegisterToSaveRestore(Alpha::R30);
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setStackPointerRegisterToSaveRestore(Alpha::R30);
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addLegalFPImmediate(APFloat(+0.0)); //F31
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addLegalFPImmediate(APFloat(+0.0f)); //F31
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addLegalFPImmediate(APFloat(-0.0)); //-F31
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addLegalFPImmediate(APFloat(-0.0f)); //-F31
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setJumpBufSize(272);
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setJumpBufSize(272);
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setJumpBufAlignment(16);
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setJumpBufAlignment(16);
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@ -919,3 +914,11 @@ AlphaTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
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// The Alpha target isn't yet aware of offsets.
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// The Alpha target isn't yet aware of offsets.
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return false;
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return false;
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}
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}
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bool AlphaTargetLowering::isFPImmLegal(const APFloat &Imm) const {
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// +0.0 F31
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// +0.0f F31
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// -0.0 -F31
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// -0.0f -F31
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return Imm.isZero() || Imm.isNegZero();
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}
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@ -102,6 +102,11 @@ namespace llvm {
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *F) const;
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virtual unsigned getFunctionAlignment(const Function *F) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm) const;
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private:
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private:
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// Helpers for custom lowering.
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// Helpers for custom lowering.
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void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
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void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
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@ -72,9 +72,6 @@ MipsTargetLowering(MipsTargetMachine &TM)
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if (!Subtarget->isFP64bit())
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if (!Subtarget->isFP64bit())
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addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
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addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
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// Legal fp constants
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addLegalFPImmediate(APFloat(+0.0f));
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// Load extented operations for i1 types must be promoted
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// Load extented operations for i1 types must be promoted
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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@ -1224,3 +1221,7 @@ MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
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// The Mips target isn't yet aware of offsets.
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// The Mips target isn't yet aware of offsets.
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return false;
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return false;
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}
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}
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bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm) const {
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return Imm.isZero();
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}
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@ -146,6 +146,11 @@ namespace llvm {
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EVT VT) const;
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EVT VT) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm) const;
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};
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};
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}
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}
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@ -53,11 +53,6 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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if (!UseSoftFloat) {
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if (!UseSoftFloat) {
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addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
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addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
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addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
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addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
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addLegalFPImmediate(APFloat(+0.0)); // lzer
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addLegalFPImmediate(APFloat(+0.0f)); // lzdr
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addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
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addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
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}
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}
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// Compute derived properties from the register classes
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// Compute derived properties from the register classes
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@ -169,6 +164,17 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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}
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}
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}
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}
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bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm) const {
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if (UseSoftFloat)
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return false;
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// +0.0 lzer
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// +0.0f lzdr
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// -0.0 lzer + lner
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// -0.0f lzdr + lndr
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return Imm.isZero() || Imm.isNegZero();
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SystemZ Inline Assembly Support
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// SystemZ Inline Assembly Support
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -89,6 +89,11 @@ namespace llvm {
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MachineBasicBlock *BB,
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MachineBasicBlock *BB,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm) const;
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private:
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private:
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SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
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SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool isVarArg,
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@ -2310,6 +2310,17 @@ static bool hasFPCMov(unsigned X86CC) {
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}
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}
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}
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}
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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bool X86TargetLowering::isFPImmLegal(const APFloat &Imm) const {
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for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
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if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
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return true;
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}
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return false;
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}
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/// isUndefOrInRange - Return true if Val is undef or if its value falls within
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/// isUndefOrInRange - Return true if Val is undef or if its value falls within
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/// the specified range (L, H].
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/// the specified range (L, H].
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static bool isUndefOrInRange(int Val, int Low, int Hi) {
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static bool isUndefOrInRange(int Val, int Low, int Hi) {
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@ -499,6 +499,11 @@ namespace llvm {
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/// from i32 to i8 but not from i32 to i16.
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/// from i32 to i8 but not from i32 to i16.
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virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
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virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm) const;
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
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@ -584,6 +589,15 @@ namespace llvm {
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bool X86ScalarSSEf32;
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bool X86ScalarSSEf32;
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bool X86ScalarSSEf64;
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bool X86ScalarSSEf64;
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/// LegalFPImmediates - A list of legal fp immediates.
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std::vector<APFloat> LegalFPImmediates;
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/// addLegalFPImmediate - Indicate that this x86 target can instruction
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/// select the specified FP immediate natively.
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void addLegalFPImmediate(const APFloat& Imm) {
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LegalFPImmediates.push_back(Imm);
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}
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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