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https://github.com/c64scene-ar/llvm-6502.git
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Encode PICADD; some code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58526 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
87e82f00ad
commit
eb4ed4b266
@ -74,8 +74,13 @@ namespace {
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unsigned getMachineSoRegOpValue(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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const MachineOperand &MO,
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unsigned OpIdx);
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unsigned getMachineSoImmOpValue(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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const MachineOperand &MO);
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unsigned getAddrMode1SBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const;
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@ -104,11 +109,10 @@ namespace {
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
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unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
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return getMachineOpValue(MI, MI.getOperand(OpIdx));
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}
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unsigned getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO);
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/// getBaseOpcodeFor - Return the opcode value.
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///
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@ -257,6 +261,70 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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MCE.emitWordLE(getInstrBinary(MI));
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}
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void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
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unsigned CPI = MI.getOperand(0).getImm();
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unsigned CPIndex = MI.getOperand(1).getIndex();
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const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIndex];
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// Remember the CONSTPOOL_ENTRY address for later relocation.
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JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
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// Emit constpool island entry. In most cases, the actual values will be
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// resolved and relocated after code emission.
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if (MCPE.isMachineConstantPoolEntry()) {
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ARMConstantPoolValue *ACPV =
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static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
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DOUT << "\t** ARM constant pool #" << CPI << ", ' @ "
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<< (void*)MCE.getCurrentPCValue() << *ACPV << '\n';
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GlobalValue *GV = ACPV->getGV();
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if (GV) {
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assert(!ACPV->isStub() && "Don't know how to deal this yet!");
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emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
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} else {
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assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
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emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
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}
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MCE.emitWordLE(0);
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} else {
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Constant *CV = MCPE.Val.ConstVal;
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DOUT << "\t** Constant pool #" << CPI << ", ' @ "
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<< (void*)MCE.getCurrentPCValue() << *CV << '\n';
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if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
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emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
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MCE.emitWordLE(0);
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} else {
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assert(CV->getType()->isInteger() &&
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"Not expecting non-integer constpool entries yet!");
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const ConstantInt *CI = dyn_cast<ConstantInt>(CV);
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uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
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MCE.emitWordLE(Val);
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}
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}
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}
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void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
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unsigned Opcode = MI.getDesc().Opcode;
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switch (Opcode) {
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default:
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abort(); // FIXME:
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case ARM::CONSTPOOL_ENTRY:
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emitConstPoolInstruction(MI);
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break;
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case ARM::PICADD: {
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// PICADD is just an add instruction that implicitly read pc.
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unsigned Binary = getBinaryCodeForInstr(MI);
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const TargetInstrDesc &TID = MI.getDesc();
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MCE.emitWordLE(getAddrMode1InstrBinary(MI, TID, Binary));
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break;
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}
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}
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}
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unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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@ -295,9 +363,9 @@ unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
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unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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const MachineOperand &MO,
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unsigned OpIdx) {
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// Set last operand (register Rm)
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unsigned Binary = getMachineOpValue(MI, OpIdx);
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unsigned Binary = getMachineOpValue(MI, MO);
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const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
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const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
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@ -351,6 +419,17 @@ unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
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return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
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}
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unsigned ARMCodeEmitter::getMachineSoImmOpValue(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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const MachineOperand &MO) {
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unsigned SoImm = MO.getImm();
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// Encode rotate_imm.
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unsigned Binary = ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
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// Encode immed_8.
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Binary |= ARM_AM::getSOImmVal(SoImm);
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return Binary;
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}
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unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const {
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for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
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@ -361,63 +440,6 @@ unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
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return 0;
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}
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void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
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unsigned CPI = MI.getOperand(0).getImm();
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unsigned CPIndex = MI.getOperand(1).getIndex();
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const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIndex];
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// Remember the CONSTPOOL_ENTRY address for later relocation.
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JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
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// Emit constpool island entry. In most cases, the actual values will be
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// resolved and relocated after code emission.
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if (MCPE.isMachineConstantPoolEntry()) {
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ARMConstantPoolValue *ACPV =
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static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
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DOUT << "\t** ARM constant pool #" << CPI << ", ' @ "
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<< (void*)MCE.getCurrentPCValue() << *ACPV << '\n';
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GlobalValue *GV = ACPV->getGV();
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if (GV) {
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assert(!ACPV->isStub() && "Don't know how to deal this yet!");
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emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
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} else {
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assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
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emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
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}
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MCE.emitWordLE(0);
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} else {
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Constant *CV = MCPE.Val.ConstVal;
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DOUT << "\t** Constant pool #" << CPI << ", ' @ "
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<< (void*)MCE.getCurrentPCValue() << *CV << '\n';
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if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
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emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
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MCE.emitWordLE(0);
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} else {
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assert(CV->getType()->isInteger() &&
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"Not expecting non-integer constpool entries yet!");
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const ConstantInt *CI = dyn_cast<ConstantInt>(CV);
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uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
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MCE.emitWordLE(Val);
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}
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}
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}
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void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
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unsigned Opcode = MI.getDesc().Opcode;
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switch (Opcode) {
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default:
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abort(); // FIXME:
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case ARM::CONSTPOOL_ENTRY: {
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emitConstPoolInstruction(MI);
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break;
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}
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}
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}
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unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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@ -437,13 +459,19 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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// Encode first non-shifter register operand if there is one.
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unsigned Format = TID.TSFlags & ARMII::FormMask;
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bool hasRnOperand= !(Format == ARMII::DPRdMisc ||
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Format == ARMII::DPRdIm ||
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Format == ARMII::DPRdReg ||
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Format == ARMII::DPRdSoReg);
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if (hasRnOperand) {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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++OpIdx;
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bool HasRnReg = !(Format == ARMII::DPRdMisc ||
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Format == ARMII::DPRdIm ||
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Format == ARMII::DPRdReg ||
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Format == ARMII::DPRdSoReg);
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if (HasRnReg) {
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if (TID.getOpcode() == ARM::PICADD)
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// Special handling for PICADD. It implicitly use add.
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Binary |=
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ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
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else {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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++OpIdx;
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}
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}
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// Encode shifter operand.
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@ -451,23 +479,20 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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Format == ARMII::DPRnSoReg ||
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Format == ARMII::DPRSoReg ||
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Format == ARMII::DPRSoRegS);
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if (HasSoReg)
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// Encode SoReg.
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return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
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const MachineOperand &MO = MI.getOperand(OpIdx);
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if (HasSoReg)
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// Encode SoReg.
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return Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx);
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if (MO.isReg())
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// Encode register Rm.
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return Binary | getMachineOpValue(MI, NumDefs);
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return Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg());
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// Encode so_imm.
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// Set bit I(25) to identify this is the immediate form of <shifter_op>
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Binary |= 1 << ARMII::I_BitShift;
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unsigned SoImm = MO.getImm();
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// Encode rotate_imm.
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Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
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// Encode immed_8.
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Binary |= ARM_AM::getSOImmVal(SoImm);
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Binary |= getMachineSoImmOpValue(MI, TID, MO);
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return Binary;
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}
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