From eb5d47d99db0d9e4fc11f136fbacbd507c71a4c2 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 7 Oct 2005 05:00:52 +0000 Subject: [PATCH] Fix a CQ regression from my patch to split F32/F64 into seperate register classes on PPC. We were emitting fmr instructions to do fp extensions, which weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstrInfo.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index dc84075eba1..2af10993554 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -57,7 +57,8 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI, destReg = MI.getOperand(0).getReg(); return true; } - } else if (oc == PPC::FMRS || oc == PPC::FMRD) { // fmr r1, r2 + } else if (oc == PPC::FMRS || oc == PPC::FMRD || + oc == PPC::FMRSD) { // fmr r1, r2 assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() &&