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ARM: check predicate bits for thumb instructions

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When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184707 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Amaury de la Vieuville 2013-06-24 09:15:01 +00:00
parent 07c3e159d8
commit ebc3938ae7
3 changed files with 35 additions and 13 deletions
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30
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -754,21 +754,25 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
return result;
}
MI.clear();
result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
UpdateThumbVFPPredicate(MI);
return result;
if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
MI.clear();
result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
UpdateThumbVFPPredicate(MI);
return result;
}
}
MI.clear();
result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
Check(result, AddThumbPredicate(MI));
return result;
if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
MI.clear();
result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
Check(result, AddThumbPredicate(MI));
return result;
}
}
if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {

9
test/MC/Disassembler/ARM/invalid-NEON-thumb.txt Normal file
View File

@ -0,0 +1,9 @@
# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
# VMOV
# RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
# VDUP
# RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
# CHECK: invalid instruction encoding

9
test/MC/Disassembler/ARM/invalid-VFP-thumb.txt Normal file
View File

@ -0,0 +1,9 @@
# VFP instructions with invalid predicate bits (pred != 0b1110)
# VABS
# RUN: echo "0x40 0xde 0x00 0x0a" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
# VMLA
# RUN: echo "0xf0 0xde 0xe0 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
# CHECK: invalid instruction encoding