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ARM: check predicate bits for thumb instructions
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and core registers, must have their predicate bit to 0b1110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184707 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -754,21 +754,25 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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return result;
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}
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MI.clear();
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result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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UpdateThumbVFPPredicate(MI);
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return result;
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if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
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MI.clear();
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result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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UpdateThumbVFPPredicate(MI);
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return result;
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}
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}
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MI.clear();
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result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
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this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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Check(result, AddThumbPredicate(MI));
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return result;
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if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
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MI.clear();
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result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
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this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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Check(result, AddThumbPredicate(MI));
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return result;
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}
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}
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if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
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9
test/MC/Disassembler/ARM/invalid-NEON-thumb.txt
Normal file
9
test/MC/Disassembler/ARM/invalid-NEON-thumb.txt
Normal file
@ -0,0 +1,9 @@
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# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
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# VMOV
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# RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
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# VDUP
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# RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
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# CHECK: invalid instruction encoding
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test/MC/Disassembler/ARM/invalid-VFP-thumb.txt
Normal file
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test/MC/Disassembler/ARM/invalid-VFP-thumb.txt
Normal file
@ -0,0 +1,9 @@
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# VFP instructions with invalid predicate bits (pred != 0b1110)
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# VABS
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# RUN: echo "0x40 0xde 0x00 0x0a" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
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# VMLA
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# RUN: echo "0xf0 0xde 0xe0 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
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# CHECK: invalid instruction encoding
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