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Lower add (mul a, b), c into MACCU / MACCS nodes which translate

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directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98150 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
2010-03-10 11:41:08 +00:00
parent 1250ac8a09
commit ebc64cf780
4 changed files with 110 additions and 0 deletions
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test/CodeGen/XCore/addsub64.ll
+24
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@@ -18,3 +18,27 @@ define i64 @sub64(i64 %a, i64 %b) {
; CHECK-NEXT: lsub r2, r0, r0, r2, r11
; CHECK-NEXT: lsub r2, r1, r1, r3, r2
; CHECK-NEXT: retsp 0
define i64 @maccu(i64 %a, i32 %b, i32 %c) {
entry:
%0 = zext i32 %b to i64
%1 = zext i32 %c to i64
%2 = mul i64 %1, %0
%3 = add i64 %2, %a
ret i64 %3
}
; CHECK: maccu:
; CHECK: maccu r1, r0, r3, r2
; CHECK-NEXT: retsp 0
define i64 @maccs(i64 %a, i32 %b, i32 %c) {
entry:
%0 = sext i32 %b to i64
%1 = sext i32 %c to i64
%2 = mul i64 %1, %0
%3 = add i64 %2, %a
ret i64 %3
}
; CHECK: maccs:
; CHECK: maccs r1, r0, r3, r2
; CHECK-NEXT: retsp 0