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R600/SI: Fix broken encoding of DS_WRITE_B32

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The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD
instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused
it to corrupt the encoding of that by clobbering the first operand with
the second one.

Undo that damage and only apply the SMRD logic to that.

Fixes some derivates related piglit regressions with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188558 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michel Danzer 2013-08-16 16:19:24 +00:00
parent ea549a847d
commit ebd4eec538
6 changed files with 24 additions and 10 deletions
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3
lib/Target/R600/SIDefines.h
View File

@ -13,7 +13,8 @@
namespace SIInstrFlags {
enum {
MIMG = 1 << 3
MIMG = 1 << 3,
SMRD = 1 << 4
};
}

19
lib/Target/R600/SIInsertWaits.cpp
View File

@ -134,14 +134,19 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
// LGKM may uses larger values
if (TSFlags & SIInstrFlags::LGKM_CNT) {
MachineOperand &Op = MI.getOperand(0);
if (!Op.isReg())
Op = MI.getOperand(1);
assert(Op.isReg() && "First LGKM operand must be a register!");
if (TII->isSMRD(MI.getOpcode())) {
unsigned Reg = Op.getReg();
unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
Result.Named.LGKM = Size > 4 ? 2 : 1;
MachineOperand &Op = MI.getOperand(0);
assert(Op.isReg() && "First LGKM operand must be a register!");
unsigned Reg = Op.getReg();
unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
Result.Named.LGKM = Size > 4 ? 2 : 1;
} else {
// DS
Result.Named.LGKM = 1;
}
} else {
Result.Named.LGKM = 0;

3
lib/Target/R600/SIInstrFormats.td
View File

@ -18,11 +18,13 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
field bits<1> EXP_CNT = 0;
field bits<1> LGKM_CNT = 0;
field bits<1> MIMG = 0;
field bits<1> SMRD = 0;
let TSFlags{0} = VM_CNT;
let TSFlags{1} = EXP_CNT;
let TSFlags{2} = LGKM_CNT;
let TSFlags{3} = MIMG;
let TSFlags{4} = SMRD;
}
class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
@ -142,6 +144,7 @@ class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
let Inst{31-27} = 0x18; //encoding
let LGKM_CNT = 1;
let SMRD = 1;
}
//===----------------------------------------------------------------------===//

4
lib/Target/R600/SIInstrInfo.cpp
View File

@ -229,6 +229,10 @@ int SIInstrInfo::isMIMG(uint16_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MIMG;
}
int SIInstrInfo::isSMRD(uint16_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SMRD;
}
//===----------------------------------------------------------------------===//
// Indirect addressing callbacks
//===----------------------------------------------------------------------===//

1
lib/Target/R600/SIInstrInfo.h
View File

@ -48,6 +48,7 @@ public:
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
int isMIMG(uint16_t Opcode) const;
int isSMRD(uint16_t Opcode) const;
virtual int getIndirectIndexBegin(const MachineFunction &MF) const;

4
test/CodeGen/R600/local-memory.ll
View File

@ -13,7 +13,7 @@
; SI-CHECK-NEXT: .long 32768
; EG-CHECK: LDS_WRITE
; SI-CHECK: DS_WRITE_B32
; SI-CHECK: DS_WRITE_B32 0
; GROUP_BARRIER must be the last instruction in a clause
; EG-CHECK: GROUP_BARRIER
@ -21,7 +21,7 @@
; SI-CHECK: S_BARRIER
; EG-CHECK: LDS_READ_RET
; SI-CHECK: DS_READ_B32
; SI-CHECK: DS_READ_B32 {{VGPR[0-9]+}}, 0
define void @local_memory(i32 addrspace(1)* %out) {
entry: