6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

more condition codes

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30567 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-09-21 13:06:26 +00:00
parent 7246d33e2a
commit ebdabda708
2 changed files with 51 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -87,7 +87,14 @@ namespace llvm {
/// DAGCCToARMCC - Convert a DAG integer condition code to an ARM CC /// DAGCCToARMCC - Convert a DAG integer condition code to an ARM CC
static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) { static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
switch (CC) { switch (CC) {
default: assert(0 && "Unknown condition code!"); default:
std::cerr << "CC = " << CC << "\n";
assert(0 && "Unknown condition code!");
case ISD::SETUGT: return ARMCC::HI;
case ISD::SETULE: return ARMCC::LS;
case ISD::SETLE: return ARMCC::LE;
case ISD::SETLT: return ARMCC::LT;
case ISD::SETGT: return ARMCC::GT;
case ISD::SETNE: return ARMCC::NE; case ISD::SETNE: return ARMCC::NE;
case ISD::SETEQ: return ARMCC::EQ; case ISD::SETEQ: return ARMCC::EQ;
case ISD::SETGE: return ARMCC::GE; case ISD::SETGE: return ARMCC::GE;

45
test/CodeGen/ARM/select.ll
View File

@ -1,8 +1,49 @@
; RUN: llvm-as < %s | llc -march=arm ; RUN: llvm-as < %s | llc -march=arm &&
; RUN: llvm-as < %s | llc -march=arm | grep moveq | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep movgt | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep movlt | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep movle | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep movls | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep movhi | wc -l | grep 1
int %f(int %a) { int %f1(int %a) {
entry: entry:
%tmp = seteq int %a, 4 ; <bool> [#uses=1] %tmp = seteq int %a, 4 ; <bool> [#uses=1]
%tmp1 = select bool %tmp, int 2, int 3 %tmp1 = select bool %tmp, int 2, int 3
ret int %tmp1 ret int %tmp1
} }
int %f2(int %a) {
entry:
%tmp = setgt int %a, 4 ; <bool> [#uses=1]
%tmp1 = select bool %tmp, int 2, int 3
ret int %tmp1
}
int %f3(int %a, int %b) {
entry:
%tmp = setlt int %a, %b ; <bool> [#uses=1]
%tmp1 = select bool %tmp, int 2, int 3
ret int %tmp1
}
int %f4(int %a, int %b) {
entry:
%tmp = setle int %a, %b ; <bool> [#uses=1]
%tmp1 = select bool %tmp, int 2, int 3
ret int %tmp1
}
int %f5(uint %a, uint %b) {
entry:
%tmp = setle uint %a, %b ; <bool> [#uses=1]
%tmp1 = select bool %tmp, int 2, int 3
ret int %tmp1
}
int %f6(uint %a, uint %b) {
entry:
%tmp = setgt uint %a, %b ; <bool> [#uses=1]
%tmp1 = select bool %tmp, int 2, int 3
ret int %tmp1
}