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[MIPS] Add cpu octeon and some instructions

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The Octeon cpu from Cavium Networks is mips64r2 based and has an extended
instruction set. In order to utilize this with LLVM, a new cpu feature "octeon"
and a subtarget feature "cnmips" is added. A small set of new instructions
(baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and
dpop instructions with option -mcpu=octeon or -mattr=+cnmips.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204337 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kai Nacke
2014-03-20 11:51:58 +00:00
parent 90844c4778
commit ebf9f0c6cb
13 changed files with 203 additions and 6 deletions
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6
lib/Target/Mips/MipsSEISelLowering.cpp
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@@ -117,10 +117,14 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::MULHS, MVT::i32, Custom);
setOperationAction(ISD::MULHU, MVT::i32, Custom);
if (Subtarget->hasCnMips())
setOperationAction(ISD::MUL, MVT::i64, Legal);
else if (HasMips64)
setOperationAction(ISD::MUL, MVT::i64, Custom);
if (HasMips64) {
setOperationAction(ISD::MULHS, MVT::i64, Custom);
setOperationAction(ISD::MULHU, MVT::i64, Custom);
setOperationAction(ISD::MUL, MVT::i64, Custom);
}
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);