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AsmMatcher/X86: Separate out sublass for memory operands that have no segment

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register, and use to cleanup a FIXME in X86AsmParser.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94859 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Dunbar 2010-01-30 00:24:00 +00:00
parent b489d0f88a
commit ec2b1f1beb
2 changed files with 19 additions and 5 deletions
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18
lib/Target/X86/AsmParser/X86AsmParser.cpp
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@ -172,6 +172,10 @@ struct X86Operand : public MCParsedAsmOperand {
bool isMem() const { return Kind == Memory; }
bool isNoSegMem() const {
return Kind == Memory && !getMemSegReg();
}
bool isReg() const { return Kind == Register; }
void addRegOperands(MCInst &Inst, unsigned N) const {
@ -191,16 +195,22 @@ struct X86Operand : public MCParsedAsmOperand {
}
void addMemOperands(MCInst &Inst, unsigned N) const {
assert((N == 4 || N == 5) && "Invalid number of operands!");
assert((N == 5) && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
Inst.addOperand(MCOperand::CreateImm(getMemScale()));
Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
}
// FIXME: What a hack.
if (N == 5)
Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
void addNoSegMemOperands(MCInst &Inst, unsigned N) const {
assert((N == 4) && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
Inst.addOperand(MCOperand::CreateImm(getMemScale()));
Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
}
static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {

6
lib/Target/X86/X86InstrInfo.td
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@ -196,6 +196,10 @@ def X86MemAsmOperand : AsmOperandClass {
let Name = "Mem";
let SuperClass = ?;
}
def X86NoSegMemAsmOperand : AsmOperandClass {
let Name = "NoSegMem";
let SuperClass = X86MemAsmOperand;
}
class X86MemOperand<string printMethod> : Operand<iPTR> {
let PrintMethod = printMethod;
let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
@ -235,7 +239,7 @@ def i8mem_NOREX : Operand<i64> {
def lea32mem : Operand<i32> {
let PrintMethod = "printlea32mem";
let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
let ParserMatchClass = X86MemAsmOperand;
let ParserMatchClass = X86NoSegMemAsmOperand;
}
def SSECC : Operand<i8> {