From ec2e968b7a60a4b48bbb315f8dd6e96e51c31691 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Tue, 19 Mar 2013 15:23:39 +0000 Subject: [PATCH] Cleanup PPC64 unaligned i64 load/store Remove an accidentally-added instruction definition and add a comment in the test case. This is in response to a post-commit review by Bill Schmidt. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177404 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstr64Bit.td | 4 ---- test/CodeGen/PowerPC/unal4-std.ll | 3 +++ 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index bca1bd50782..724c2bd7ad6 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -683,10 +683,6 @@ def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), "ldx $rD, $src", LdStLD, [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; -let isCodeGenOnly = 1 in -def LDXu : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), - "ldx $rD, $src", LdStLD, - [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; let mayLoad = 1 in def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), diff --git a/test/CodeGen/PowerPC/unal4-std.ll b/test/CodeGen/PowerPC/unal4-std.ll index dc4c20cc3fe..169bd787c0c 100644 --- a/test/CodeGen/PowerPC/unal4-std.ll +++ b/test/CodeGen/PowerPC/unal4-std.ll @@ -17,6 +17,9 @@ vector.body.i: ; preds = %vector.body.i, %if. if.end210: ; preds = %entry ret void +; This will generate two align-1 i64 stores. Make sure that they are +; indexed stores and not in r+i form (which require the offset to be +; a multiple of 4). ; CHECK: @copy_to_conceal ; CHECK: stdx {{[0-9]+}}, 0, }