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PTX: Fix whitespace errors

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133158 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski 2011-06-16 15:17:11 +00:00
parent d381a7a91e
commit ec3141b27f
4 changed files with 27 additions and 25 deletions
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19
lib/Target/PTX/PTXAsmPrinter.cpp
View File

@ -311,7 +311,7 @@ void PTXAsmPrinter::EmitVariableDeclaration(const GlobalVariable *gv) {
decl += ".b8 ";
decl += gvsym->getName();
decl += "[";
if (elementTy->isArrayTy())
{
assert(elementTy->isArrayTy() && "Only pointers to arrays are supported");
@ -320,7 +320,7 @@ void PTXAsmPrinter::EmitVariableDeclaration(const GlobalVariable *gv) {
elementTy = arrayTy->getElementType();
unsigned numElements = arrayTy->getNumElements();
while (elementTy->isArrayTy()) {
arrayTy = dyn_cast<const ArrayType>(elementTy);
@ -336,14 +336,14 @@ void PTXAsmPrinter::EmitVariableDeclaration(const GlobalVariable *gv) {
// Compute the size of the array, in bytes.
uint64_t arraySize = (elementTy->getPrimitiveSizeInBits() >> 3)
* numElements;
decl += utostr(arraySize);
}
decl += "]";
// handle string constants (assume ConstantArray means string)
if (gv->hasInitializer())
{
Constant *C = gv->getInitializer();
@ -354,10 +354,11 @@ void PTXAsmPrinter::EmitVariableDeclaration(const GlobalVariable *gv) {
for (unsigned i = 0, e = C->getNumOperands(); i != e; ++i)
{
if (i > 0) decl += ",";
decl += "0x" + utohexstr(cast<ConstantInt>(CA->getOperand(i))->getZExtValue());
decl += "0x" +
utohexstr(cast<ConstantInt>(CA->getOperand(i))->getZExtValue());
}
decl += "}";
}
}

18
lib/Target/PTX/PTXISelLowering.cpp
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@ -35,22 +35,22 @@ PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
addRegisterClass(MVT::f64, PTX::RRegf64RegisterClass);
setBooleanContents(ZeroOrOneBooleanContent);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
// Turn i16 (z)extload into load + (z)extend
setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
// Turn f32 extload into load + fextend
setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
// Turn f64 truncstore into trunc + store.
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// Customize translation of memory addresses
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
@ -62,7 +62,7 @@ PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
// need to lower SETCC of Preds into bitwise logic
setOperationAction(ISD::SETCC, MVT::i1, Custom);
@ -113,18 +113,18 @@ SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
SDValue Op2 = Op.getOperand(2);
DebugLoc dl = Op.getDebugLoc();
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
// Look for X == 0, X == 1, X != 0, or X != 1
// We can simplify these to bitwise logic
if (Op1.getOpcode() == ISD::Constant &&
(cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
cast<ConstantSDNode>(Op1)->isNullValue()) &&
(CC == ISD::SETEQ || CC == ISD::SETNE)) {
return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1);
return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1);
}
return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
}

6
lib/Target/PTX/PTXISelLowering.h
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@ -40,7 +40,7 @@ class PTXTargetLowering : public TargetLowering {
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
virtual SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
virtual SDValue
LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
@ -58,9 +58,9 @@ class PTXTargetLowering : public TargetLowering {
const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl,
SelectionDAG &DAG) const;
virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
private:
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
}; // class PTXTargetLowering

9
lib/Target/PTX/PTXSubtarget.h
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@ -49,10 +49,11 @@ namespace llvm {
// The native .f64 type is supported on the hardware.
bool SupportsDouble;
// Support the fused-multiply add (FMA) and multiply-add (MAD) instructions
// Support the fused-multiply add (FMA) and multiply-add (MAD)
// instructions
bool SupportsFMA;
// Use .u64 instead of .u32 for addresses.
bool Is64Bit;
@ -68,7 +69,7 @@ namespace llvm {
bool is64Bit() const { return Is64Bit; }
bool supportsFMA() const { return SupportsFMA; }
bool supportsSM13() const { return PTXShaderModel >= PTX_SM_1_3; }
bool supportsSM20() const { return PTXShaderModel >= PTX_SM_2_0; }