mirror of
https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Use a ComplexPattern for DS loads and stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216278 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
80544654f3
commit
ec4cb3346d
@ -88,6 +88,9 @@ private:
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SDValue& Offset);
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bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
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unsigned OffsetBits) const;
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bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
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void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
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SDValue &SOffset, SDValue &Offset, SDValue &Offen,
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SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
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@ -744,6 +747,41 @@ SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
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return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
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}
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bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
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unsigned OffsetBits) const {
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
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(OffsetBits == 8 && !isUInt<8>(Offset)))
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return false;
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if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
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return true;
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// On Southern Islands instruction with a negative base value and an offset
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// don't seem to work.
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return CurDAG->SignBitIsZero(Base);
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}
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bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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SDValue N0 = Addr.getOperand(0);
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SDValue N1 = Addr.getOperand(1);
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ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
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if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
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// (add n0, c0)
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Base = N0;
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Offset = N1;
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return true;
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}
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}
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// default case
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i16);
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return true;
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}
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static SDValue wrapAddr64Rsrc(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
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return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32,
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Ptr), 0);
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@ -191,6 +191,8 @@ def tfe : Operand <i1> {
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// Complex patterns
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//===----------------------------------------------------------------------===//
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def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
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def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
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def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
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def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
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@ -2520,41 +2520,27 @@ def : ROTRPattern <V_ALIGNBIT_B32>;
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/********** Load/Store Patterns **********/
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/********** ======================= **********/
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multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
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def : Pat <
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(vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
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(inst (i1 0), $ptr, (as_i16imm $offset))
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>;
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class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
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(vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
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(inst (i1 0), $ptr, (as_i16imm $offset))
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>;
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def : Pat <
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(frag i32:$src0),
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(vt (inst 0, $src0, 0))
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>;
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}
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def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
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def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
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def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
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def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
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def : DSReadPat <DS_READ_B32, i32, local_load>;
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def : DSReadPat <DS_READ_B64, v2i32, local_load>;
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defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
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defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
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defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
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defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
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defm : DSReadPat <DS_READ_B32, i32, local_load>;
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defm : DSReadPat <DS_READ_B64, v2i32, local_load>;
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class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
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(frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
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(inst (i1 0), $ptr, $value, (as_i16imm $offset))
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>;
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multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
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def : Pat <
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(frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
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(inst (i1 0), $ptr, $value, (as_i16imm $offset))
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>;
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def : Pat <
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(frag vt:$val, i32:$ptr),
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(inst 0, $ptr, $val, 0)
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>;
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}
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defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
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defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
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defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
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defm : DSWritePat <DS_WRITE_B64, v2i32, local_store>;
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def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
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def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
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def : DSWritePat <DS_WRITE_B32, i32, local_store>;
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def : DSWritePat <DS_WRITE_B64, v2i32, local_store>;
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multiclass DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> {
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def : Pat <
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=CI --check-prefix=FUNC %s
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; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
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; the global address space(1) uses 64-bit pointers. These tests check to make sure
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@ -9,7 +10,7 @@
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; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
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; instructions with B64, U64, and I64 take 64-bit operands.
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; CHECK-LABEL: @local_address_load
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; FUNC-LABEL: @local_address_load
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; CHECK: V_MOV_B32_e{{32|64}} [[PTR:v[0-9]]]
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; CHECK: DS_READ_B32 v{{[0-9]+}}, [[PTR]]
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define void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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@ -19,7 +20,7 @@ entry:
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ret void
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}
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; CHECK-LABEL: @local_address_gep
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; FUNC-LABEL: @local_address_gep
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; CHECK: S_ADD_I32 [[SPTR:s[0-9]]]
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; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; CHECK: DS_READ_B32 [[VPTR]]
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@ -31,7 +32,7 @@ entry:
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ret void
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}
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; CHECK-LABEL: @local_address_gep_const_offset
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; FUNC-LABEL: @local_address_gep_const_offset
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; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
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; CHECK: DS_READ_B32 v{{[0-9]+}}, [[VPTR]], 0x4,
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define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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@ -43,7 +44,7 @@ entry:
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}
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; Offset too large, can't fold into 16-bit immediate offset.
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; CHECK-LABEL: @local_address_gep_large_const_offset
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; FUNC-LABEL: @local_address_gep_large_const_offset
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; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
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; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; CHECK: DS_READ_B32 [[VPTR]]
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@ -55,7 +56,7 @@ entry:
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ret void
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}
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; CHECK-LABEL: @null_32bit_lds_ptr:
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; FUNC-LABEL: @null_32bit_lds_ptr:
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; CHECK: V_CMP_NE_I32
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; CHECK-NOT: V_CMP_NE_I32
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; CHECK: V_CNDMASK_B32
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@ -66,7 +67,7 @@ define void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds)
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ret void
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}
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; CHECK-LABEL: @mul_32bit_ptr:
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; FUNC-LABEL: @mul_32bit_ptr:
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; CHECK: V_MUL_LO_I32
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; CHECK-NEXT: V_ADD_I32_e32
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; CHECK-NEXT: DS_READ_B32
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@ -79,7 +80,7 @@ define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %
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@g_lds = addrspace(3) global float zeroinitializer, align 4
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; CHECK-LABEL: @infer_ptr_alignment_global_offset:
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; FUNC-LABEL: @infer_ptr_alignment_global_offset:
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; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0
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; CHECK: DS_READ_B32 v{{[0-9]+}}, [[REG]]
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define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
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@ -92,21 +93,21 @@ define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %ti
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@ptr = addrspace(3) global i32 addrspace(3)* null
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@dst = addrspace(3) global [16384 x i32] zeroinitializer
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; CHECK-LABEL: @global_ptr:
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; FUNC-LABEL: @global_ptr:
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; CHECK: DS_WRITE_B32
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define void @global_ptr() nounwind {
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store i32 addrspace(3)* getelementptr ([16384 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr
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ret void
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}
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; CHECK-LABEL: @local_address_store
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; FUNC-LABEL: @local_address_store
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; CHECK: DS_WRITE_B32
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define void @local_address_store(i32 addrspace(3)* %out, i32 %val) {
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store i32 %val, i32 addrspace(3)* %out
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ret void
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}
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; CHECK-LABEL: @local_address_gep_store
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; FUNC-LABEL: @local_address_gep_store
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; CHECK: S_ADD_I32 [[SADDR:s[0-9]+]],
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; CHECK: V_MOV_B32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
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; CHECK: DS_WRITE_B32 [[ADDR]], v{{[0-9]+}},
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@ -116,7 +117,7 @@ define void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32
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ret void
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}
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; CHECK-LABEL: @local_address_gep_const_offset_store
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; FUNC-LABEL: @local_address_gep_const_offset_store
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; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
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; CHECK: V_MOV_B32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
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; CHECK: DS_WRITE_B32 [[VPTR]], [[VAL]], 0x4
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@ -127,7 +128,7 @@ define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %v
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}
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; Offset too large, can't fold into 16-bit immediate offset.
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; CHECK-LABEL: @local_address_gep_large_const_offset_store
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; FUNC-LABEL: @local_address_gep_large_const_offset_store
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; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
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; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; CHECK: DS_WRITE_B32 [[VPTR]], v{{[0-9]+}}, 0
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@ -1,18 +1,29 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s
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; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
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declare i32 @llvm.r600.read.tidig.x() #0
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declare void @llvm.AMDGPU.barrier.local() #1
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; Function Attrs: nounwind
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; SI-LABEL: @signed_ds_offset_addressing_loop
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; SI: BB0_1:
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; SI: V_ADD_I32_e32 [[VADDR:v[0-9]+]],
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; CHECK-LABEL: @signed_ds_offset_addressing_loop
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; CHECK: BB0_1:
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; CHECK: V_ADD_I32_e32 [[VADDR:v[0-9]+]],
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x0
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x4
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x80
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x84
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x100
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; SI: S_ENDPGM
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; SI-DAG: V_ADD_I32_e32 [[VADDR4:v[0-9]+]], 4, [[VADDR]]
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR4]], 0x0
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; SI-DAG: V_ADD_I32_e32 [[VADDR0x80:v[0-9]+]], 0x80, [[VADDR]]
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x80]], 0x0
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; SI-DAG: V_ADD_I32_e32 [[VADDR0x84:v[0-9]+]], 0x84, [[VADDR]]
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x84]], 0x0
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; SI-DAG: V_ADD_I32_e32 [[VADDR0x100:v[0-9]+]], 0x100, [[VADDR]]
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x100]], 0x0
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; CI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x0
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; CI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x4
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; CI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x80
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; CI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x84
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; CI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x100
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; CHECK: S_ENDPGM
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define void @signed_ds_offset_addressing_loop(float addrspace(1)* noalias nocapture %out, float addrspace(3)* noalias nocapture readonly %lptr, i32 %n) #2 {
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entry:
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #0
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@ -1,4 +1,5 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck %s
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s
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; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
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define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
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; CHECK-LABEL: @use_gep_address_space:
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@ -11,7 +12,10 @@ define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
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define void @use_gep_address_space_large_offset([1024 x i32] addrspace(3)* %array) nounwind {
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; CHECK-LABEL: @use_gep_address_space_large_offset:
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; CHECK: S_ADD_I32
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; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
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; SI, which is why it is being OR'd with the base pointer.
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; SI: S_OR_B32
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; CI: S_ADD_I32
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; CHECK: DS_WRITE_B32
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%p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16384
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store i32 99, i32 addrspace(3)* %p
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@ -1,8 +1,9 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=BOTH %s
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; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s
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; SI-LABEL: @local_i32_load
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; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x1c, [M0]
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; SI: BUFFER_STORE_DWORD [[REG]],
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; BOTH-LABEL: @local_i32_load
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; BOTH: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x1c, [M0]
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; BOTH: BUFFER_STORE_DWORD [[REG]],
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define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
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%gep = getelementptr i32 addrspace(3)* %in, i32 7
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%val = load i32 addrspace(3)* %gep, align 4
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@ -10,19 +11,19 @@ define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounw
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ret void
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}
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; SI-LABEL: @local_i32_load_0_offset
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; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x0, [M0]
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; SI: BUFFER_STORE_DWORD [[REG]],
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; BOTH-LABEL: @local_i32_load_0_offset
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; BOTH: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x0, [M0]
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; BOTH: BUFFER_STORE_DWORD [[REG]],
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define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
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%val = load i32 addrspace(3)* %in, align 4
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store i32 %val, i32 addrspace(1)* %out, align 4
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||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_i8_load_i16_max_offset
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_READ_U8 [[REG:v[0-9]+]], {{v[0-9]+}}, 0xffff, [M0]
|
||||
; SI: BUFFER_STORE_BYTE [[REG]],
|
||||
; BOTH-LABEL: @local_i8_load_i16_max_offset
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: DS_READ_U8 [[REG:v[0-9]+]], {{v[0-9]+}}, 0xffff, [M0]
|
||||
; BOTH: BUFFER_STORE_BYTE [[REG]],
|
||||
define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i8 addrspace(3)* %in, i32 65535
|
||||
%val = load i8 addrspace(3)* %gep, align 4
|
||||
@ -30,11 +31,14 @@ define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_i8_load_over_i16_max_offset
|
||||
; SI: S_ADD_I32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
|
||||
; SI: V_MOV_B32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
|
||||
; SI: DS_READ_U8 [[REG:v[0-9]+]], [[VREGADDR]], 0x0, [M0]
|
||||
; SI: BUFFER_STORE_BYTE [[REG]],
|
||||
; BOTH-LABEL: @local_i8_load_over_i16_max_offset
|
||||
; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
|
||||
; SI, which is why it is being OR'd with the base pointer.
|
||||
; SI: S_OR_B32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
|
||||
; CI: S_ADD_I32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
|
||||
; BOTH: V_MOV_B32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
|
||||
; BOTH: DS_READ_U8 [[REG:v[0-9]+]], [[VREGADDR]], 0x0, [M0]
|
||||
; BOTH: BUFFER_STORE_BYTE [[REG]],
|
||||
define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i8 addrspace(3)* %in, i32 65536
|
||||
%val = load i8 addrspace(3)* %gep, align 4
|
||||
@ -42,10 +46,10 @@ define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspa
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_i64_load
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
|
||||
; SI: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
; BOTH-LABEL: @local_i64_load
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
|
||||
; BOTH: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i64 addrspace(3)* %in, i32 7
|
||||
%val = load i64 addrspace(3)* %gep, align 8
|
||||
@ -53,19 +57,19 @@ define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounw
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_i64_load_0_offset
|
||||
; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
|
||||
; SI: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
; BOTH-LABEL: @local_i64_load_0_offset
|
||||
; BOTH: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
|
||||
; BOTH: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
|
||||
%val = load i64 addrspace(3)* %in, align 8
|
||||
store i64 %val, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_f64_load
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
|
||||
; SI: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
; BOTH-LABEL: @local_f64_load
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
|
||||
; BOTH: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr double addrspace(3)* %in, i32 7
|
||||
%val = load double addrspace(3)* %gep, align 8
|
||||
@ -73,85 +77,85 @@ define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in)
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_f64_load_0_offset
|
||||
; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
|
||||
; SI: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
; BOTH-LABEL: @local_f64_load_0_offset
|
||||
; BOTH: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
|
||||
; BOTH: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
|
||||
%val = load double addrspace(3)* %in, align 8
|
||||
store double %val, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_i64_store
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
|
||||
; BOTH-LABEL: @local_i64_store
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
|
||||
define void @local_i64_store(i64 addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr i64 addrspace(3)* %out, i32 7
|
||||
store i64 5678, i64 addrspace(3)* %gep, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_i64_store_0_offset
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
; BOTH-LABEL: @local_i64_store_0_offset
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
|
||||
store i64 1234, i64 addrspace(3)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_f64_store
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
|
||||
; BOTH-LABEL: @local_f64_store
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
|
||||
define void @local_f64_store(double addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr double addrspace(3)* %out, i32 7
|
||||
store double 16.0, double addrspace(3)* %gep, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_f64_store_0_offset
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
; BOTH-LABEL: @local_f64_store_0_offset
|
||||
; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
|
||||
store double 20.0, double addrspace(3)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_v2i64_store
|
||||
; SI-NOT: ADD
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x78 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x70 [M0]
|
||||
; BOTH-LABEL: @local_v2i64_store
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x78 [M0]
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x70 [M0]
|
||||
define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr <2 x i64> addrspace(3)* %out, i32 7
|
||||
store <2 x i64> <i64 5678, i64 5678>, <2 x i64> addrspace(3)* %gep, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_v2i64_store_0_offset
|
||||
; SI-NOT: ADD
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
; BOTH-LABEL: @local_v2i64_store_0_offset
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
|
||||
store <2 x i64> <i64 1234, i64 1234>, <2 x i64> addrspace(3)* %out, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_v4i64_store
|
||||
; SI-NOT: ADD
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf0 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe0 [M0]
|
||||
; BOTH-LABEL: @local_v4i64_store
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf8 [M0]
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf0 [M0]
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe8 [M0]
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe0 [M0]
|
||||
define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr <4 x i64> addrspace(3)* %out, i32 7
|
||||
store <4 x i64> <i64 5678, i64 5678, i64 5678, i64 5678>, <4 x i64> addrspace(3)* %gep, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_v4i64_store_0_offset
|
||||
; SI-NOT: ADD
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x18 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x10 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
; BOTH-LABEL: @local_v4i64_store_0_offset
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x18 [M0]
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x10 [M0]
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
|
||||
; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
define void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind {
|
||||
store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, <4 x i64> addrspace(3)* %out, align 16
|
||||
ret void
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
|
||||
; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
|
||||
; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=SI %s
|
||||
; RUN: llc < %s -march=r600 -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=CI %s
|
||||
|
||||
@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] zeroinitializer, align 4
|
||||
@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] zeroinitializer, align 4
|
||||
@ -28,8 +29,10 @@
|
||||
; constant offsets.
|
||||
; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
|
||||
; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
|
||||
; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]], 0x10
|
||||
; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]], 0x0,
|
||||
; SI: V_ADD_I32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}}
|
||||
; SI: DS_READ_B32 {{v[0-9]+}}, [[SIPTR]], 0x0
|
||||
; CI: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]], 0x10
|
||||
; CI: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]], 0x0,
|
||||
|
||||
define void @local_memory_two_objects(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user