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The Thumb2 RFE instructions need to have their second halfword fully specified.

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In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-04-12 21:41:51 +00:00
parent 5db4289e40
commit ec51a6225c
3 changed files with 14 additions and 6 deletions
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8
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@@ -1142,8 +1142,12 @@ static bool DisassembleThumb2SRS(MCInst &MI, unsigned Opcode, uint32_t insn,
// t2RFE[IA|DB]W/t2RFE[IA|DB]: Rn
static bool DisassembleThumb2RFE(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRn(insn))));
unsigned Rn = decodeRn(insn);
if (Rn == 15) {
DEBUG(errs() << "if n == 15 then UNPREDICTABLE\n");
return false;
}
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,ARM::GPRRegClassID,Rn)));
NumOpsAdded = 1;
return true;
}