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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/). Change all ELF tests to ELF32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -41,10 +41,10 @@ def CC_PPC : CallingConv<[
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
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// Darwin passes FP values in F1 - F13
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// Common sub-targets passes FP values in F1 - F13
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CCIfType<[f32, f64], CCIfSubtarget<"isMachoABI()",
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CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>>,
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// Other sub-targets pass FP values in F1-F8.
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// ELF32 sub-target pass FP values in F1 - F8.
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CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
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// The first 12 Vector arguments are passed in altivec registers.
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@ -32,8 +32,8 @@ public:
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static unsigned getReturnSaveOffset(bool LP64, bool isMacho) {
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if (isMacho)
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return LP64 ? 16 : 8;
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// For ELF ABI:
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return LP64 ? 8 : 4;
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// For ELF 32 ABI:
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return 4;
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}
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/// getFramePointerSaveOffset - Return the previous frame offset to save the
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@ -46,9 +46,9 @@ public:
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if (isMacho)
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return LP64 ? 40 : 20;
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// For ELF ABI:
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// For ELF 32 ABI:
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// Save it right before the link register
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return LP64 ? -8 : -4;
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return -4;
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}
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/// getLinkageSize - Return the size of the PowerPC ABI linkage area.
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@ -57,8 +57,8 @@ public:
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if (isMacho)
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return 6 * (LP64 ? 8 : 4);
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// For ELF ABI:
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return LP64 ? 16 : 8;
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// For ELF 32 ABI:
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return 8;
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}
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/// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
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@ -73,7 +73,7 @@ public:
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if (isMacho)
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return 8 * (LP64 ? 8 : 4);
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// For Linux ABI:
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// For ELF 32 ABI:
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// There is no default stack allocated for the 8 first GPR arguments.
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return 0;
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}
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@ -1132,7 +1132,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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bool isPPC64 = PtrVT == MVT::i64;
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bool isMachoABI = Subtarget.isMachoABI();
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bool isELF_ABI = Subtarget.isELF_ABI();
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bool isELF32_ABI = Subtarget.isELF32_ABI();
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unsigned PtrByteSize = isPPC64 ? 8 : 4;
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unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
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@ -1165,7 +1165,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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// entry to a function on PPC, the arguments start after the linkage area,
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// although the first ones are often in registers.
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//
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// In the ELF ABI, GPRs and stack are double word align: an argument
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// In the ELF 32 ABI, GPRs and stack are double word align: an argument
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// represented with two words (long long or double) must be copied to an
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// even GPR_idx value or to an even ArgOffset value.
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@ -1187,7 +1187,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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default: assert(0 && "Unhandled argument type!");
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case MVT::i32:
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// Double word align in ELF
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if (Expand && isELF_ABI && !isPPC64) GPR_idx += (GPR_idx % 2);
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if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
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if (GPR_idx != Num_GPR_Regs) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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@ -1198,7 +1198,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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ArgSize = PtrByteSize;
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}
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// Stack align in ELF
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if (needsLoad && Expand && isELF_ABI && !isPPC64)
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if (needsLoad && Expand && isELF32_ABI)
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ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
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// All int arguments reserve stack space in Macho ABI.
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if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
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@ -1240,7 +1240,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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}
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// Stack align in ELF
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if (needsLoad && Expand && isELF_ABI && !isPPC64)
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if (needsLoad && Expand && isELF32_ABI)
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ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
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// All FP arguments reserve stack space in Macho ABI.
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if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
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@ -1344,7 +1344,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
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unsigned NumOps = (Op.getNumOperands() - 5) / 2;
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bool isMachoABI = Subtarget.isMachoABI();
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bool isELF_ABI = Subtarget.isELF_ABI();
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bool isELF32_ABI = Subtarget.isELF32_ABI();
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MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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bool isPPC64 = PtrVT == MVT::i64;
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@ -1432,8 +1432,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
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// register cannot be found for it.
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SDOperand PtrOff;
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// Stack align in ELF
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if (isELF_ABI && Expand && !isPPC64)
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// Stack align in ELF 32
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if (isELF32_ABI && Expand)
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PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
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StackPtr.getValueType());
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else
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@ -1453,7 +1453,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
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case MVT::i32:
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case MVT::i64:
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// Double word align in ELF
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if (isELF_ABI && Expand && !isPPC64) GPR_idx += (GPR_idx % 2);
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if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
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if (GPR_idx != NumGPRs) {
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RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
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} else {
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@ -1462,7 +1462,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
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}
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if (inMem || isMachoABI) {
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// Stack align in ELF
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if (isELF_ABI && Expand && !isPPC64)
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if (isELF32_ABI && Expand)
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ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
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ArgOffset += PtrByteSize;
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@ -1516,7 +1516,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
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}
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if (inMem || isMachoABI) {
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// Stack align in ELF
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if (isELF_ABI && Expand && !isPPC64)
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if (isELF32_ABI && Expand)
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ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
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if (isPPC64)
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ArgOffset += 8;
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@ -1548,8 +1548,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
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InFlag = Chain.getValue(1);
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}
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// With the ELF ABI, set CR6 to true if this is a vararg call.
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if (isVarArg && isELF_ABI) {
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// With the ELF 32 ABI, set CR6 to true if this is a vararg call.
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if (isVarArg && isELF32_ABI) {
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SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
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Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
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InFlag = Chain.getValue(1);
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@ -87,11 +87,12 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7,
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"bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
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}
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// ELF ABI Calls.
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// ELF 64 ABI Calls = Macho ABI Calls
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// Used to define BL8_ELF and BLA8_ELF
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let isCall = 1, noResults = 1, PPC970_Unit = 7,
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// All calls clobber the PPC64 non-callee saved registers.
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Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
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F0,F1,F2,F3,F4,F5,F6,F7,F8,
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F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
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V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
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LR8,CTR8,
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CR0,CR1,CR5,CR6,CR7] in {
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@ -250,7 +250,7 @@ void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
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const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
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// 32-bit Darwin calling convention.
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static const unsigned Darwin32_CalleeSavedRegs[] = {
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static const unsigned Macho32_CalleeSavedRegs[] = {
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PPC::R13, PPC::R14, PPC::R15,
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PPC::R16, PPC::R17, PPC::R18, PPC::R19,
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PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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@ -294,7 +294,7 @@ const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
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PPC::LR, 0
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};
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// 64-bit Darwin calling convention.
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static const unsigned Darwin64_CalleeSavedRegs[] = {
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static const unsigned Macho64_CalleeSavedRegs[] = {
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PPC::X14, PPC::X15,
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PPC::X16, PPC::X17, PPC::X18, PPC::X19,
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PPC::X20, PPC::X21, PPC::X22, PPC::X23,
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@ -315,41 +315,18 @@ const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
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PPC::LR8, 0
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};
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static const unsigned ELF64_CalleeSavedRegs[] = {
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PPC::X14, PPC::X15,
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PPC::X16, PPC::X17, PPC::X18, PPC::X19,
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PPC::X20, PPC::X21, PPC::X22, PPC::X23,
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PPC::X24, PPC::X25, PPC::X26, PPC::X27,
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PPC::X28, PPC::X29, PPC::X30, PPC::X31,
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PPC::F9,
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PPC::F10, PPC::F11, PPC::F12, PPC::F13,
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PPC::F14, PPC::F15, PPC::F16, PPC::F17,
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PPC::F18, PPC::F19, PPC::F20, PPC::F21,
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PPC::F22, PPC::F23, PPC::F24, PPC::F25,
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PPC::F26, PPC::F27, PPC::F28, PPC::F29,
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PPC::F30, PPC::F31,
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PPC::CR2, PPC::CR3, PPC::CR4,
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PPC::V20, PPC::V21, PPC::V22, PPC::V23,
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PPC::V24, PPC::V25, PPC::V26, PPC::V27,
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PPC::V28, PPC::V29, PPC::V30, PPC::V31,
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PPC::LR8, 0
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};
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if (Subtarget.isMachoABI())
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return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
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Darwin32_CalleeSavedRegs;
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return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
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Macho32_CalleeSavedRegs;
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// ELF.
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return Subtarget.isPPC64() ? ELF64_CalleeSavedRegs : ELF32_CalleeSavedRegs;
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// ELF 32.
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return ELF32_CalleeSavedRegs;
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}
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const TargetRegisterClass* const*
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PPCRegisterInfo::getCalleeSavedRegClasses() const {
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// 32-bit Darwin calling convention.
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static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
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// 32-bit Macho calling convention.
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static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
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&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
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&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
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&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
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@ -395,8 +372,8 @@ PPCRegisterInfo::getCalleeSavedRegClasses() const {
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&PPC::GPRCRegClass, 0
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};
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// 64-bit Darwin calling convention.
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static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
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// 64-bit Macho calling convention.
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static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
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&PPC::G8RCRegClass,&PPC::G8RCRegClass,
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&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
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&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
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@ -418,37 +395,12 @@ PPCRegisterInfo::getCalleeSavedRegClasses() const {
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&PPC::G8RCRegClass, 0
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};
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static const TargetRegisterClass * const ELF64_CalleeSavedRegClasses[] = {
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&PPC::G8RCRegClass,&PPC::G8RCRegClass,
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&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
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&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
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&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
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&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
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&PPC::F8RCRegClass,
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&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
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&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
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&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
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&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
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&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
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&PPC::F8RCRegClass,&PPC::F8RCRegClass,
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&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
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&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
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&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
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&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
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&PPC::G8RCRegClass, 0
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};
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if (Subtarget.isMachoABI())
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return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
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Darwin32_CalleeSavedRegClasses;
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return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
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Macho32_CalleeSavedRegClasses;
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// ELF.
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return Subtarget.isPPC64() ? ELF64_CalleeSavedRegClasses :
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ELF32_CalleeSavedRegClasses;
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// ELF 32.
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return ELF32_CalleeSavedRegClasses;
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}
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// needsFP - Return true if the specified function should have a dedicated frame
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@ -900,15 +852,16 @@ void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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// Save R31 if necessary
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int FPSI = FI->getFramePointerSaveIndex();
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bool IsPPC64 = Subtarget.isPPC64();
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bool IsELF_ABI = Subtarget.isELF_ABI();
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bool IsELF32_ABI = Subtarget.isELF32_ABI();
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bool IsMachoABI = Subtarget.isMachoABI();
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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// If the frame pointer save index hasn't been defined yet.
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if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects())
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&& IsELF_ABI) {
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&& IsELF32_ABI) {
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// Find out what the fix offset of the frame pointer save area.
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int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
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!IsELF_ABI);
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int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
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IsMachoABI);
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// Allocate the frame index for frame pointer save area.
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FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
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// Save the result.
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@ -134,8 +134,8 @@ public:
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bool isDarwin() const { return IsDarwin; }
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bool isMachoABI() const { return IsDarwin; }
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bool isELF_ABI() const { return !IsDarwin; }
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bool isMachoABI() const { return IsDarwin || IsPPC64; }
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bool isELF32_ABI() const { return !IsDarwin && !IsPPC64; }
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unsigned getAsmFlavor() const {
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return AsmFlavor != Unset ? unsigned(AsmFlavor) : 0;
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