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[AArch64 NEON] Get instruction BSL matched to VSELECT.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196998 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin
2013-12-11 02:33:50 +00:00
parent 8514590ee9
commit ec5ebdec47
3 changed files with 17 additions and 24 deletions
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11
lib/Target/AArch64/AArch64ISelLowering.cpp
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@@ -941,8 +941,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
case AArch64ISD::WrapperSmall: return "AArch64ISD::WrapperSmall";
case AArch64ISD::NEON_BSL:
return "AArch64ISD::NEON_BSL";
case AArch64ISD::NEON_MOVIMM:
return "AArch64ISD::NEON_MOVIMM";
case AArch64ISD::NEON_MVNIMM:
@@ -3434,12 +3432,9 @@ static SDValue PerformORCombine(SDNode *N,
if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
HasAnyUndefs) &&
!HasAnyUndefs && SplatBits0 == ~SplatBits1) {
// Canonicalize the vector type to make instruction selection simpler.
EVT CanonicalVT = VT.is128BitVector() ? MVT::v16i8 : MVT::v8i8;
SDValue Result = DAG.getNode(AArch64ISD::NEON_BSL, DL, CanonicalVT,
N0->getOperand(1), N0->getOperand(0),
N1->getOperand(0));
return DAG.getNode(ISD::BITCAST, DL, VT, Result);
return DAG.getNode(ISD::VSELECT, DL, VT, N0->getOperand(1),
N0->getOperand(0), N1->getOperand(0));
}
}
}