mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-20 11:29:24 +00:00
* Differentiate between global and weak symbol loads
* Fix functions that take more than 32 bytes of args * Alignment of doubles in structs is 4 bytes, not 8 * Fix passing long args: rN = hi, rN+1 = lo * Rewrite signed divide * Rewrite Intrinsic::returnaddress Patch courtesy of Nate Begeman. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15036 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -75,7 +75,6 @@ namespace {
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MachineFunction *F; // The function we are compiling into
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MachineBasicBlock *BB; // The current MBB we are compiling
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int VarArgsFrameIndex; // FrameIndex for start of varargs area
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int ReturnAddressIndex; // FrameIndex for the return address
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std::map<Value*, unsigned> RegMap; // Mapping between Values and SSA Regs
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@ -143,10 +142,6 @@ namespace {
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BB = &F->front();
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// Set up a frame object for the return address. This is used by the
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// llvm.returnaddress & llvm.frameaddress intrinisics.
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ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
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// Copy incoming arguments off of the stack...
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LoadArgumentsToVirtualRegs(Fn);
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@ -517,7 +512,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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// Move value at PC + distance into return reg
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BuildMI(*MBB, IP, PPC32::LOADHiAddr, 2, Reg1).addReg(CurPC)
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.addConstantPoolIndex(CPI);
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BuildMI(*MBB, IP, PPC32::LOADLoAddr, 2, Reg2).addReg(Reg1)
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BuildMI(*MBB, IP, PPC32::LOADLoDirect, 2, Reg2).addReg(Reg1)
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.addConstantPoolIndex(CPI);
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unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
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@ -529,13 +524,16 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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// GV is located at PC + distance
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unsigned CurPC = makeAnotherReg(Type::IntTy);
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unsigned TmpReg = makeAnotherReg(GV->getType());
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unsigned Opcode = GV->hasWeakLinkage() ?
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PPC32::LOADLoIndirect :
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PPC32::LOADLoDirect;
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// Move PC to destination reg
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BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC);
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// Move value at PC + distance into return reg
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BuildMI(*MBB, IP, PPC32::LOADHiAddr, 2, TmpReg).addReg(CurPC)
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.addGlobalAddress(GV);
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BuildMI(*MBB, IP, PPC32::LOADLoAddr, 2, R).addReg(TmpReg)
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.addGlobalAddress(GV);
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BuildMI(*MBB, IP, Opcode, 2, R).addReg(TmpReg).addGlobalAddress(GV);
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} else {
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std::cerr << "Offending constant: " << *C << "\n";
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assert(0 && "Type not handled yet!");
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@ -548,7 +546,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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/// FIXME: When we can calculate which args are coming in via registers
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/// source them from there instead.
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void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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unsigned ArgOffset = 20; // FIXME why is this not 24?
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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unsigned GPR_idx = 0, FPR_idx = 0;
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@ -571,7 +569,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
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switch (getClassB(I->getType())) {
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case cByte:
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if (ArgLive) {
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FI = MFI->CreateFixedObject(1, ArgOffset);
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FI = MFI->CreateFixedObject(4, ArgOffset);
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if (GPR_remaining > 0) {
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BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
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@ -583,7 +581,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
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break;
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case cShort:
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if (ArgLive) {
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FI = MFI->CreateFixedObject(2, ArgOffset);
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FI = MFI->CreateFixedObject(4, ArgOffset);
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if (GPR_remaining > 0) {
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BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
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@ -1397,12 +1395,13 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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case cLong:
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ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
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// Reg or stack?
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// Reg or stack? Note that PPC calling conventions state that long args
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// are passed rN = hi, rN+1 = lo, opposite of LLVM.
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if (GPR_remaining > 1) {
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
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.addReg(ArgReg);
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx+1]).addReg(ArgReg+1)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg+1)
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.addReg(ArgReg+1);
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx+1]).addReg(ArgReg)
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.addReg(ArgReg);
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CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
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CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
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} else {
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@ -1502,9 +1501,9 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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case cFP64:
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BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
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break;
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case cLong: // Long values are in r3:r4
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BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
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BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R4).addReg(PPC32::R4);
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case cLong: // Long values are in r3 hi:r4 lo
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BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R3).addReg(PPC32::R3);
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BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R4).addReg(PPC32::R4);
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break;
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default: assert(0 && "Unknown class!");
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}
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@ -1624,7 +1623,8 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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case Intrinsic::vastart:
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// Get the address of the first vararg value...
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TmpReg1 = getReg(CI);
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addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex);
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addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex,
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0, false);
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return;
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case Intrinsic::vacopy:
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@ -1635,17 +1635,23 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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case Intrinsic::vaend: return;
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case Intrinsic::returnaddress:
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TmpReg1 = getReg(CI);
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if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
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MachineFrameInfo *MFI = F->getFrameInfo();
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unsigned NumBytes = MFI->getStackSize();
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BuildMI(BB, PPC32::LWZ, 2, TmpReg1).addImm(NumBytes+8)
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.addReg(PPC32::R1);
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} else {
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// Values other than zero are not implemented yet.
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BuildMI(BB, PPC32::LI, 1, TmpReg1).addImm(0);
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}
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return;
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case Intrinsic::frameaddress:
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TmpReg1 = getReg(CI);
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if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
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if (ID == Intrinsic::returnaddress) {
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// Just load the return address
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addFrameReference(BuildMI(BB, PPC32::LWZ, 2, TmpReg1),
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ReturnAddressIndex);
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} else {
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addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1),
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ReturnAddressIndex, -4, false);
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}
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BuildMI(BB, PPC32::OR, 2, TmpReg1).addReg(PPC32::R1).addReg(PPC32::R1);
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} else {
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// Values other than zero are not implemented yet.
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BuildMI(BB, PPC32::LI, 1, TmpReg1).addImm(0);
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@ -2172,54 +2178,29 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
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return;
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}
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bool isNeg = false;
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if (V < 0) { // Not a positive power of 2?
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V = -V;
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isNeg = true; // Maybe it's a negative power of 2.
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}
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if (unsigned Log = ExactLog2(V)) {
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--Log;
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unsigned log2V = ExactLog2(V);
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if (log2V != 0 && Ty->isSigned()) {
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unsigned Op0Reg = getReg(Op0, BB, IP);
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unsigned TmpReg = makeAnotherReg(Op0->getType());
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if (Log != 1)
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BuildMI(*BB, IP, PPC32::SRAWI,2, TmpReg).addReg(Op0Reg).addImm(Log-1);
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else
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BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(Op0Reg).addReg(Op0Reg);
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unsigned TmpReg2 = makeAnotherReg(Op0->getType());
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BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg2).addReg(TmpReg).addImm(Log)
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.addImm(32-Log).addImm(31);
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unsigned TmpReg3 = makeAnotherReg(Op0->getType());
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BuildMI(*BB, IP, PPC32::ADD, 2, TmpReg3).addReg(Op0Reg).addReg(TmpReg2);
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unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
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BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg4).addReg(Op0Reg).addImm(Log);
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if (isNeg)
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BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(TmpReg4);
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BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg).addReg(Op0Reg)
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.addImm(log2V-1);
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BuildMI(*BB, IP, PPC32::ADDZE, 1, ResultReg).addReg(TmpReg);
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return;
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}
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}
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unsigned Op0Reg = getReg(Op0, BB, IP);
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unsigned Op1Reg = getReg(Op1, BB, IP);
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unsigned Opcode = Ty->isSigned() ? PPC32::DIVW : PPC32::DIVWU;
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if (isDiv) {
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if (Ty->isSigned()) {
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BuildMI(*BB, IP, PPC32::DIVW, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
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} else {
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BuildMI(*BB, IP,PPC32::DIVWU, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
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}
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BuildMI(*BB, IP, Opcode, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
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} else { // Remainder
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unsigned TmpReg1 = makeAnotherReg(Op0->getType());
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unsigned TmpReg2 = makeAnotherReg(Op0->getType());
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if (Ty->isSigned()) {
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BuildMI(*BB, IP, PPC32::DIVW, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
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} else {
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BuildMI(*BB, IP, PPC32::DIVWU, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
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}
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BuildMI(*BB, IP, Opcode, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, IP, PPC32::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
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BuildMI(*BB, IP, PPC32::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
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}
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@ -2690,11 +2671,11 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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if (DestClass == cByte) {
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unsigned TempReg2 = makeAnotherReg(DestTy);
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addFrameReference(BuildMI(*BB, IP, LoadOp, 2, TempReg2),
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ValueFrameIdx+4);
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ValueFrameIdx, 4);
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BuildMI(*MBB, IP, PPC32::EXTSB, DestReg).addReg(TempReg2);
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} else {
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addFrameReference(BuildMI(*BB, IP, LoadOp, 2, DestReg),
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ValueFrameIdx+4);
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ValueFrameIdx, 4);
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}
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} else {
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std::cerr << "Cast fp-to-unsigned not implemented!";
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@ -75,7 +75,6 @@ namespace {
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MachineFunction *F; // The function we are compiling into
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MachineBasicBlock *BB; // The current MBB we are compiling
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int VarArgsFrameIndex; // FrameIndex for start of varargs area
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int ReturnAddressIndex; // FrameIndex for the return address
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std::map<Value*, unsigned> RegMap; // Mapping between Values and SSA Regs
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@ -143,10 +142,6 @@ namespace {
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BB = &F->front();
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// Set up a frame object for the return address. This is used by the
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// llvm.returnaddress & llvm.frameaddress intrinisics.
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ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
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// Copy incoming arguments off of the stack...
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LoadArgumentsToVirtualRegs(Fn);
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@ -517,7 +512,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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// Move value at PC + distance into return reg
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BuildMI(*MBB, IP, PPC32::LOADHiAddr, 2, Reg1).addReg(CurPC)
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.addConstantPoolIndex(CPI);
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BuildMI(*MBB, IP, PPC32::LOADLoAddr, 2, Reg2).addReg(Reg1)
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BuildMI(*MBB, IP, PPC32::LOADLoDirect, 2, Reg2).addReg(Reg1)
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.addConstantPoolIndex(CPI);
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unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
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@ -529,13 +524,16 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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// GV is located at PC + distance
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unsigned CurPC = makeAnotherReg(Type::IntTy);
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unsigned TmpReg = makeAnotherReg(GV->getType());
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unsigned Opcode = GV->hasWeakLinkage() ?
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PPC32::LOADLoIndirect :
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PPC32::LOADLoDirect;
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// Move PC to destination reg
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BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC);
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// Move value at PC + distance into return reg
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BuildMI(*MBB, IP, PPC32::LOADHiAddr, 2, TmpReg).addReg(CurPC)
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.addGlobalAddress(GV);
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BuildMI(*MBB, IP, PPC32::LOADLoAddr, 2, R).addReg(TmpReg)
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.addGlobalAddress(GV);
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BuildMI(*MBB, IP, Opcode, 2, R).addReg(TmpReg).addGlobalAddress(GV);
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} else {
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std::cerr << "Offending constant: " << *C << "\n";
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assert(0 && "Type not handled yet!");
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@ -548,7 +546,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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/// FIXME: When we can calculate which args are coming in via registers
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/// source them from there instead.
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void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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unsigned ArgOffset = 20; // FIXME why is this not 24?
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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unsigned GPR_idx = 0, FPR_idx = 0;
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@ -571,7 +569,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
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switch (getClassB(I->getType())) {
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case cByte:
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if (ArgLive) {
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FI = MFI->CreateFixedObject(1, ArgOffset);
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FI = MFI->CreateFixedObject(4, ArgOffset);
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if (GPR_remaining > 0) {
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BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
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@ -583,7 +581,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
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break;
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case cShort:
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if (ArgLive) {
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FI = MFI->CreateFixedObject(2, ArgOffset);
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FI = MFI->CreateFixedObject(4, ArgOffset);
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if (GPR_remaining > 0) {
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BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
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@ -1397,12 +1395,13 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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case cLong:
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ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
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// Reg or stack?
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// Reg or stack? Note that PPC calling conventions state that long args
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// are passed rN = hi, rN+1 = lo, opposite of LLVM.
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if (GPR_remaining > 1) {
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
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.addReg(ArgReg);
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx+1]).addReg(ArgReg+1)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg+1)
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.addReg(ArgReg+1);
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx+1]).addReg(ArgReg)
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.addReg(ArgReg);
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CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
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CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
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} else {
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@ -1502,9 +1501,9 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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case cFP64:
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BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
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break;
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case cLong: // Long values are in r3:r4
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BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
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BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R4).addReg(PPC32::R4);
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case cLong: // Long values are in r3 hi:r4 lo
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BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R3).addReg(PPC32::R3);
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BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R4).addReg(PPC32::R4);
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break;
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default: assert(0 && "Unknown class!");
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}
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@ -1624,7 +1623,8 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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case Intrinsic::vastart:
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// Get the address of the first vararg value...
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TmpReg1 = getReg(CI);
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addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex);
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addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex,
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0, false);
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return;
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case Intrinsic::vacopy:
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@ -1635,17 +1635,23 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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case Intrinsic::vaend: return;
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case Intrinsic::returnaddress:
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TmpReg1 = getReg(CI);
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if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
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MachineFrameInfo *MFI = F->getFrameInfo();
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unsigned NumBytes = MFI->getStackSize();
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|
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BuildMI(BB, PPC32::LWZ, 2, TmpReg1).addImm(NumBytes+8)
|
||||
.addReg(PPC32::R1);
|
||||
} else {
|
||||
// Values other than zero are not implemented yet.
|
||||
BuildMI(BB, PPC32::LI, 1, TmpReg1).addImm(0);
|
||||
}
|
||||
return;
|
||||
|
||||
case Intrinsic::frameaddress:
|
||||
TmpReg1 = getReg(CI);
|
||||
if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
|
||||
if (ID == Intrinsic::returnaddress) {
|
||||
// Just load the return address
|
||||
addFrameReference(BuildMI(BB, PPC32::LWZ, 2, TmpReg1),
|
||||
ReturnAddressIndex);
|
||||
} else {
|
||||
addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1),
|
||||
ReturnAddressIndex, -4, false);
|
||||
}
|
||||
BuildMI(BB, PPC32::OR, 2, TmpReg1).addReg(PPC32::R1).addReg(PPC32::R1);
|
||||
} else {
|
||||
// Values other than zero are not implemented yet.
|
||||
BuildMI(BB, PPC32::LI, 1, TmpReg1).addImm(0);
|
||||
@ -2172,54 +2178,29 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
|
||||
return;
|
||||
}
|
||||
|
||||
bool isNeg = false;
|
||||
if (V < 0) { // Not a positive power of 2?
|
||||
V = -V;
|
||||
isNeg = true; // Maybe it's a negative power of 2.
|
||||
}
|
||||
if (unsigned Log = ExactLog2(V)) {
|
||||
--Log;
|
||||
unsigned log2V = ExactLog2(V);
|
||||
if (log2V != 0 && Ty->isSigned()) {
|
||||
unsigned Op0Reg = getReg(Op0, BB, IP);
|
||||
unsigned TmpReg = makeAnotherReg(Op0->getType());
|
||||
if (Log != 1)
|
||||
BuildMI(*BB, IP, PPC32::SRAWI,2, TmpReg).addReg(Op0Reg).addImm(Log-1);
|
||||
else
|
||||
BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(Op0Reg).addReg(Op0Reg);
|
||||
|
||||
unsigned TmpReg2 = makeAnotherReg(Op0->getType());
|
||||
BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg2).addReg(TmpReg).addImm(Log)
|
||||
.addImm(32-Log).addImm(31);
|
||||
|
||||
unsigned TmpReg3 = makeAnotherReg(Op0->getType());
|
||||
BuildMI(*BB, IP, PPC32::ADD, 2, TmpReg3).addReg(Op0Reg).addReg(TmpReg2);
|
||||
|
||||
unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
|
||||
BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg4).addReg(Op0Reg).addImm(Log);
|
||||
|
||||
if (isNeg)
|
||||
BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(TmpReg4);
|
||||
|
||||
BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg).addReg(Op0Reg)
|
||||
.addImm(log2V-1);
|
||||
BuildMI(*BB, IP, PPC32::ADDZE, 1, ResultReg).addReg(TmpReg);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned Op0Reg = getReg(Op0, BB, IP);
|
||||
unsigned Op1Reg = getReg(Op1, BB, IP);
|
||||
|
||||
unsigned Opcode = Ty->isSigned() ? PPC32::DIVW : PPC32::DIVWU;
|
||||
|
||||
if (isDiv) {
|
||||
if (Ty->isSigned()) {
|
||||
BuildMI(*BB, IP, PPC32::DIVW, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
|
||||
} else {
|
||||
BuildMI(*BB, IP,PPC32::DIVWU, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
|
||||
}
|
||||
BuildMI(*BB, IP, Opcode, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
|
||||
} else { // Remainder
|
||||
unsigned TmpReg1 = makeAnotherReg(Op0->getType());
|
||||
unsigned TmpReg2 = makeAnotherReg(Op0->getType());
|
||||
|
||||
if (Ty->isSigned()) {
|
||||
BuildMI(*BB, IP, PPC32::DIVW, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
|
||||
} else {
|
||||
BuildMI(*BB, IP, PPC32::DIVWU, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
|
||||
}
|
||||
BuildMI(*BB, IP, Opcode, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
|
||||
BuildMI(*BB, IP, PPC32::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
|
||||
BuildMI(*BB, IP, PPC32::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
|
||||
}
|
||||
@ -2690,11 +2671,11 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
|
||||
if (DestClass == cByte) {
|
||||
unsigned TempReg2 = makeAnotherReg(DestTy);
|
||||
addFrameReference(BuildMI(*BB, IP, LoadOp, 2, TempReg2),
|
||||
ValueFrameIdx+4);
|
||||
ValueFrameIdx, 4);
|
||||
BuildMI(*MBB, IP, PPC32::EXTSB, DestReg).addReg(TempReg2);
|
||||
} else {
|
||||
addFrameReference(BuildMI(*BB, IP, LoadOp, 2, DestReg),
|
||||
ValueFrameIdx+4);
|
||||
ValueFrameIdx, 4);
|
||||
}
|
||||
} else {
|
||||
std::cerr << "Cast fp-to-unsigned not implemented!";
|
||||
|
Loading…
Reference in New Issue
Block a user