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Some permute goodness for A9

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100664 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2010-04-07 18:21:22 +00:00
parent 5ca13c6ee3
commit ec69dfa7ca
1 changed files with 85 additions and 1 deletions
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86
lib/Target/ARM/ARMScheduleV7.td
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@ -1014,9 +1014,93 @@ def CortexA9Itineraries : ProcessorItineraries<[
// Quad-register Integer Multiply-Accumulate (.32)
InstrItinData<IIC_VMACi32Q, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 9 cycles
InstrStage2<10, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<4, [FU_NPipe]>], [9, 3, 2, 1]>,
//
// Double-register Permute
InstrItinData<IIC_VPERMD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 6 cycles
InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [2, 2, 1, 1]>,
//
// Quad-register Permute
// Result written in N2, but that is relative to the last cycle of multicycle,
// so we use 3 for those cases
InstrItinData<IIC_VPERMQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 7 cycles
InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<4, [FU_NPipe]>], [9, 3, 2, 1]>
InstrStage<2, [FU_NPipe]>], [3, 3, 1, 1]>,
//
// Quad-register Permute (3 cycle issue)
// Result written in N2, but that is relative to the last cycle of multicycle,
// so we use 4 for those cases
InstrItinData<IIC_VPERMQ3, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 8 cycles
InstrStage2<9, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<3, [FU_NLSPipe]>], [4, 4, 1, 1]>,
//
// Double-register VEXT
InstrItinData<IIC_VEXTD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 7 cycles
InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [2, 1, 1]>,
//
// Quad-register VEXT
InstrItinData<IIC_VEXTQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 9 cycles
InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<2, [FU_NPipe]>], [3, 1, 1]>,
//
// VTB
InstrItinData<IIC_VTB1, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 7 cycles
InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<2, [FU_NPipe]>], [3, 2, 1]>,
InstrItinData<IIC_VTB2, [InstrStage2<2, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 7 cycles
InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<2, [FU_NPipe]>], [3, 2, 2, 1]>,
InstrItinData<IIC_VTB3, [InstrStage2<2, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 8 cycles
InstrStage2<9, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<3, [FU_NPipe]>], [4, 2, 2, 3, 1]>,
InstrItinData<IIC_VTB4, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 8 cycles
InstrStage2<9, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<3, [FU_NPipe]>], [4, 2, 2, 3, 3, 1]>,
//
// VTBX
InstrItinData<IIC_VTBX1, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 7 cycles
InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<2, [FU_NPipe]>], [3, 1, 2, 1]>,
InstrItinData<IIC_VTBX2, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 7 cycles
InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<2, [FU_NPipe]>], [3, 1, 2, 2, 1]>,
InstrItinData<IIC_VTBX3, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 8 cycles
InstrStage2<9, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<3, [FU_NPipe]>], [4, 1, 2, 2, 3, 1]>,
InstrItinData<IIC_VTBX4, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 8 cycles
InstrStage2<9, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<2, [FU_NPipe]>], [4, 1, 2, 2, 3, 3, 1]>
]>;