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clang-format a bit of code to make the next patch easier to read.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203203 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2014-03-07 05:32:03 +00:00
parent 49dd5e831b
commit ec7ab53570
3 changed files with 99 additions and 115 deletions
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46
include/llvm/CodeGen/MachineOperand.h
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@ -43,22 +43,22 @@ class MCSymbol;
class MachineOperand { class MachineOperand {
public: public:
enum MachineOperandType { enum MachineOperandType {
MO_Register, ///< Register operand. MO_Register, ///< Register operand.
MO_Immediate, ///< Immediate operand MO_Immediate, ///< Immediate operand
MO_CImmediate, ///< Immediate >64bit operand MO_CImmediate, ///< Immediate >64bit operand
MO_FPImmediate, ///< Floating-point immediate operand MO_FPImmediate, ///< Floating-point immediate operand
MO_MachineBasicBlock, ///< MachineBasicBlock reference MO_MachineBasicBlock, ///< MachineBasicBlock reference
MO_FrameIndex, ///< Abstract Stack Frame Index MO_FrameIndex, ///< Abstract Stack Frame Index
MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
MO_TargetIndex, ///< Target-dependent index+offset operand. MO_TargetIndex, ///< Target-dependent index+offset operand.
MO_JumpTableIndex, ///< Address of indexed Jump Table for switch MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
MO_ExternalSymbol, ///< Name of external global symbol MO_ExternalSymbol, ///< Name of external global symbol
MO_GlobalAddress, ///< Address of a global value MO_GlobalAddress, ///< Address of a global value
MO_BlockAddress, ///< Address of a basic block MO_BlockAddress, ///< Address of a basic block
MO_RegisterMask, ///< Mask of preserved registers. MO_RegisterMask, ///< Mask of preserved registers.
MO_RegisterLiveOut, ///< Mask of live-out registers. MO_RegisterLiveOut, ///< Mask of live-out registers.
MO_Metadata, ///< Metadata reference (for debug info) MO_Metadata, ///< Metadata reference (for debug info)
MO_MCSymbol ///< MCSymbol reference (for debug/eh info) MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
}; };
private: private:
@ -150,13 +150,13 @@ private:
/// Contents union - This contains the payload for the various operand types. /// Contents union - This contains the payload for the various operand types.
union { union {
MachineBasicBlock *MBB; // For MO_MachineBasicBlock. MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
const ConstantFP *CFP; // For MO_FPImmediate. const ConstantFP *CFP; // For MO_FPImmediate.
const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit. const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
int64_t ImmVal; // For MO_Immediate. int64_t ImmVal; // For MO_Immediate.
const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut. const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
const MDNode *MD; // For MO_Metadata. const MDNode *MD; // For MO_Metadata.
MCSymbol *Sym; // For MO_MCSymbol MCSymbol *Sym; // For MO_MCSymbol
struct { // For MO_Register. struct { // For MO_Register.
// Register number is in SmallContents.RegNo. // Register number is in SmallContents.RegNo.

142
include/llvm/Target/TargetOpcodes.h
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@ -22,90 +22,90 @@ namespace llvm {
/// must be the same as in CodeGenTarget.cpp. /// must be the same as in CodeGenTarget.cpp.
/// ///
namespace TargetOpcode { namespace TargetOpcode {
enum { enum {
PHI = 0, PHI = 0,
INLINEASM = 1, INLINEASM = 1,
PROLOG_LABEL = 2, PROLOG_LABEL = 2,
EH_LABEL = 3, EH_LABEL = 3,
GC_LABEL = 4, GC_LABEL = 4,
/// KILL - This instruction is a noop that is used only to adjust the /// KILL - This instruction is a noop that is used only to adjust the
/// liveness of registers. This can be useful when dealing with /// liveness of registers. This can be useful when dealing with
/// sub-registers. /// sub-registers.
KILL = 5, KILL = 5,
/// EXTRACT_SUBREG - This instruction takes two operands: a register /// EXTRACT_SUBREG - This instruction takes two operands: a register
/// that has subregisters, and a subregister index. It returns the /// that has subregisters, and a subregister index. It returns the
/// extracted subregister value. This is commonly used to implement /// extracted subregister value. This is commonly used to implement
/// truncation operations on target architectures which support it. /// truncation operations on target architectures which support it.
EXTRACT_SUBREG = 6, EXTRACT_SUBREG = 6,
/// INSERT_SUBREG - This instruction takes three operands: a register that /// INSERT_SUBREG - This instruction takes three operands: a register that
/// has subregisters, a register providing an insert value, and a /// has subregisters, a register providing an insert value, and a
/// subregister index. It returns the value of the first register with the /// subregister index. It returns the value of the first register with the
/// value of the second register inserted. The first register is often /// value of the second register inserted. The first register is often
/// defined by an IMPLICIT_DEF, because it is commonly used to implement /// defined by an IMPLICIT_DEF, because it is commonly used to implement
/// anyext operations on target architectures which support it. /// anyext operations on target architectures which support it.
INSERT_SUBREG = 7, INSERT_SUBREG = 7,
/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
IMPLICIT_DEF = 8, IMPLICIT_DEF = 8,
/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
/// the first operand is an immediate integer constant. This constant is /// the first operand is an immediate integer constant. This constant is
/// often zero, because it is commonly used to assert that the instruction /// often zero, because it is commonly used to assert that the instruction
/// defining the register implicitly clears the high bits. /// defining the register implicitly clears the high bits.
SUBREG_TO_REG = 9, SUBREG_TO_REG = 9,
/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
/// register-to-register copy into a specific register class. This is only /// register-to-register copy into a specific register class. This is only
/// used between instruction selection and MachineInstr creation, before /// used between instruction selection and MachineInstr creation, before
/// virtual registers have been created for all the instructions, and it's /// virtual registers have been created for all the instructions, and it's
/// only needed in cases where the register classes implied by the /// only needed in cases where the register classes implied by the
/// instructions are insufficient. It is emitted as a COPY MachineInstr. /// instructions are insufficient. It is emitted as a COPY MachineInstr.
COPY_TO_REGCLASS = 10, COPY_TO_REGCLASS = 10,
/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
DBG_VALUE = 11, DBG_VALUE = 11,
/// REG_SEQUENCE - This variadic instruction is used to form a register that /// REG_SEQUENCE - This variadic instruction is used to form a register that
/// represents a consecutive sequence of sub-registers. It's used as a /// represents a consecutive sequence of sub-registers. It's used as a
/// register coalescing / allocation aid and must be eliminated before code /// register coalescing / allocation aid and must be eliminated before code
/// emission. /// emission.
// In SDNode form, the first operand encodes the register class created by // In SDNode form, the first operand encodes the register class created by
// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
// pair. Once it has been lowered to a MachineInstr, the regclass operand // pair. Once it has been lowered to a MachineInstr, the regclass operand
// is no longer present. // is no longer present.
/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
/// After register coalescing references of v1024 should be replace with /// After register coalescing references of v1024 should be replace with
/// v1027:3, v1025 with v1027:4, etc. /// v1027:3, v1025 with v1027:4, etc.
REG_SEQUENCE = 12, REG_SEQUENCE = 12,
/// COPY - Target-independent register copy. This instruction can also be /// COPY - Target-independent register copy. This instruction can also be
/// used to copy between subregisters of virtual registers. /// used to copy between subregisters of virtual registers.
COPY = 13, COPY = 13,
/// BUNDLE - This instruction represents an instruction bundle. Instructions /// BUNDLE - This instruction represents an instruction bundle. Instructions
/// which immediately follow a BUNDLE instruction which are marked with /// which immediately follow a BUNDLE instruction which are marked with
/// 'InsideBundle' flag are inside the bundle. /// 'InsideBundle' flag are inside the bundle.
BUNDLE = 14, BUNDLE = 14,
/// Lifetime markers. /// Lifetime markers.
LIFETIME_START = 15, LIFETIME_START = 15,
LIFETIME_END = 16, LIFETIME_END = 16,
/// A Stackmap instruction captures the location of live variables at its /// A Stackmap instruction captures the location of live variables at its
/// position in the instruction stream. It is followed by a shadow of bytes /// position in the instruction stream. It is followed by a shadow of bytes
/// that must lie within the function and not contain another stackmap. /// that must lie within the function and not contain another stackmap.
STACKMAP = 17, STACKMAP = 17,
/// Patchable call instruction - this instruction represents a call to a /// Patchable call instruction - this instruction represents a call to a
/// constant address, followed by a series of NOPs. It is intended to /// constant address, followed by a series of NOPs. It is intended to
/// support optimizations for dynamic languages (such as javascript) that /// support optimizations for dynamic languages (such as javascript) that
/// rewrite calls to runtimes with more efficient code sequences. /// rewrite calls to runtimes with more efficient code sequences.
/// This also implies a stack map. /// This also implies a stack map.
PATCHPOINT = 18 PATCHPOINT = 18
}; };
} // end namespace TargetOpcode } // end namespace TargetOpcode
} // end namespace llvm } // end namespace llvm

26
utils/TableGen/CodeGenTarget.cpp
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@ -294,27 +294,11 @@ GetInstByName(const char *Name,
void CodeGenTarget::ComputeInstrsByEnum() const { void CodeGenTarget::ComputeInstrsByEnum() const {
// The ordering here must match the ordering in TargetOpcodes.h. // The ordering here must match the ordering in TargetOpcodes.h.
static const char *const FixedInstrs[] = { static const char *const FixedInstrs[] = {
"PHI", "PHI", "INLINEASM", "PROLOG_LABEL", "EH_LABEL",
"INLINEASM", "GC_LABEL", "KILL", "EXTRACT_SUBREG", "INSERT_SUBREG",
"PROLOG_LABEL", "IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE",
"EH_LABEL", "REG_SEQUENCE", "COPY", "BUNDLE", "LIFETIME_START",
"GC_LABEL", "LIFETIME_END", "STACKMAP", "PATCHPOINT", 0};
"KILL",
"EXTRACT_SUBREG",
"INSERT_SUBREG",
"IMPLICIT_DEF",
"SUBREG_TO_REG",
"COPY_TO_REGCLASS",
"DBG_VALUE",
"REG_SEQUENCE",
"COPY",
"BUNDLE",
"LIFETIME_START",
"LIFETIME_END",
"STACKMAP",
"PATCHPOINT",
0
};
const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions(); const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
for (const char *const *p = FixedInstrs; *p; ++p) { for (const char *const *p = FixedInstrs; *p; ++p) {
const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);