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Thumb parsing and encoding for SVC.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138360 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-23 19:49:10 +00:00
parent 414b02357a
commit ec8b866434
3 changed files with 21 additions and 1 deletions
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2
lib/Target/ARM/ARMInstrThumb.td
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@ -534,7 +534,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
}
// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
// A8.6.218 Supervisor Call (Software Interrupt)
// A8.6.16 B: Encoding T1
// If Inst{11-8} == 0b1111 then SEE SVC
let isCall = 1, Uses = [SP] in

10
test/MC/ARM/basic-thumb-instructions.s
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@ -533,3 +533,13 @@ _func:
subs r1, r2, r3
@ CHECK: subs r1, r2, r3 @ encoding: [0xd1,0x1a]
@------------------------------------------------------------------------------
@ SVC
@------------------------------------------------------------------------------
svc #0
svc #255
@ CHECK: svc #0 @ encoding: [0x00,0xdf]
@ CHECK: svc #255 @ encoding: [0xff,0xdf]

10
test/MC/ARM/thumb-diagnostics.s
View File

@ -108,3 +108,13 @@ error: invalid operand for instruction
@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
@ CHECK-ERRORS: str r3, [r7, #128]
@ CHECK-ERRORS: ^
@ Out of range immediate for SVC instruction.
svc #-1
svc #256
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: svc #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
@ CHECK-ERRORS: svc #256
@ CHECK-ERRORS: ^