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Move the various Subtarget dependent members down to the subtarget

Browse Source 
for the Sparc port. Use the same initializeSubtargetDependencies
function to handle initialization similar to the other ports to
handle dependencies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211811 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2014-06-26 22:33:55 +00:00
parent 9e50640808
commit eca517deaa
4 changed files with 81 additions and 65 deletions
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32
lib/Target/Sparc/SparcTargetMachine.cpp
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@ -23,32 +23,6 @@ extern "C" void LLVMInitializeSparcTarget() {
RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
}
static std::string computeDataLayout(const SparcSubtarget &ST) {
// Sparc is big endian.
std::string Ret = "E-m:e";
// Some ABIs have 32bit pointers.
if (!ST.is64Bit())
Ret += "-p:32:32";
// Alignments for 64 bit integers.
Ret += "-i64:64";
// On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
// On SparcV9 registers can hold 64 or 32 bits, on others only 32.
if (ST.is64Bit())
Ret += "-n32:64";
else
Ret += "-f128:64-n32";
if (ST.is64Bit())
Ret += "-S128";
else
Ret += "-S64";
return Ret;
}
/// SparcTargetMachine ctor - Create an ILP32 architecture model
///
SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
@ -58,11 +32,7 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL,
bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, is64bit),
DL(computeDataLayout(Subtarget)),
InstrInfo(Subtarget),
TLInfo(*this), TSInfo(DL),
FrameLowering(Subtarget) {
Subtarget(TT, CPU, FS, *this, is64bit) {
initAsmInfo();
}